SAN JOSE, Calif. - In 1999, 0.25-micron design seems poised to leave the domain of the power users and enter the ASIC and IC design mainstream. But most observers agree that while 0.25-micron design is rapidly becoming more accessible, there are still gaps in tools and methodologies that make it a continuing challenge.
Users who have completed 0.25-micron designs have generally done well, but they're reporting stumbling blocks in at least three key areas: a lack of design planning or floor-planning tools, difficulty with parasitic extraction and back-annotation and the huge memory requirements of verification tools.
They're also finding that interconnect delays, crosstalk and electromigration are becoming more problematic.On the plus side, many ASIC and third-party vendors introduced 0.25-micron libraries in 1997, and both existing EDA vendors and startups have announced progress with synthesis, verification, and IC layout and extraction tools. ASIC vendors and foundries claim to be moving into the 0.25-micron era without undue difficulty.
Bryan Lewis, principal semiconductor analyst at Dataquest Inc. (San Jose), said 34.1 percent of North American ASIC design starts will be at 0.25 micron this year-a big jump over the 14.1 percent that Dataquest forecast for 1998. "I think we're seeing a natural migration to 0.25 micron," Lewis said. "Yes, there are a few issues to be worked out, but in 1999 we see it going mainstream."
Problems in yield?
A more dour assessment comes from Lewis' colleague Gary Smith, principal EDA analyst at Dataquest. He said that very little 0.25-micron work is going on outside of FPGAs and memories, and that signal-integrity and electromigration problems are slashing 0.25-micron yields to as low as 30 to 40 percent-a claim emphatically denied by ASIC vendors and foundries.
Smith also said that the "ASIC mainstream" is disappearing and that the focus is shifting to an "ASIC light" model that includes foundries, library providers and third-party design services. However, he did say that IBM, LSI Logic and Texas Instruments are among the ASIC vendors that are doing well with 0.25-micron design.
As feature sizes shrink, the definition of an ASIC as opposed to a custom IC gets blurry. Many chip designers who might have turned over gate-level net-lists to ASIC vendors in the past are doing their own layout through customer-owned tooling (COT), and using foundries instead.
Lara Technology (San Jose), for instance, recently finished a 0.25-micron design for a high-density memory IC. It includes a full-custom core, but Lara used ASIC tools and a COT methodology to build the wrap-around logic, said Ajit Medhekar, Lara's president.
"Our partner in this first [0.25-micron] program was IBM," Medhekar said. "We feel they are most certainly ready for it, not only in terms of product performance but also in terms of manufacturability."
But there are still some weak areas in the 0.25-micron design flow, he said. One is back-annotation of timing data between physical and logical design. Another is floor planning, which can help reduce iterations between layout and synthesis. "We could have benefited from better floor-planning tools," said Medhekar. "We didn't have them, so we did a lot of it manually."
Jayan Ramankutti, vice president of engineering at Lara, said current parasitic extraction tools were sufficient for Lara's 66-MHz design. But to get maximum performance out of 0.25-micron designs, better capacitance and resistance extraction and back-annotation tools are needed, he said.
To avoid electromigration and crosstalk, Ramankutti said, "we followed [IBM] rules very, very carefully. Following their rule set pretty much guaranteed we would not have these issues."
When Lara started its project, the availability of 0.25-micron libraries was a problem. So Lara worked closely with Duet Technologies (San Jose) to migrate Duet's 0.35-micron standard-cell library to 0.25 micron.
Another successful 0.25-micron project was recently completed at Nvidia (Santa Clara, Calif.). Engineers there completed a 1.5 million-gate ASIC graphics processor design with relatively few problems, said Chris Malachowsky, vice president of engineering.
Nvidia used libraries from Artisan Components (Sunnyvale, Calif.), did its own layout with the Apollo tools from Avant! Corp. (Fremont, Calif.) and went to Taiwan Semiconductor Manufacturing Corp. (TSMC) for fabrication. Verification tools came from Cadence, Synopsys and Ikos.
Malachowsky said interconnect delays were a more significant percentage of total delay at 0.25 micron. As a result, he said, "we've put some restrictions on fanout and we've constrained our module boundaries. We have some rules we're following, and we spent time characterizing wire loads."
The most difficult challenge of 0.25 micron, said Malachowsky, is the sheer size of the designs and the databases they require. "I think we're actually at the point where next-generation devices are in real trouble," he said. "We've already found almost an inability to back-annotate in simulation. We can no longer just read in SDF [Standard Delay Format]."
Centillium Technology Corp. (Sunnyvale, Calif.) recently completed a 0.25-micron design for its new Copper Lite digital subscriber line (DSL) chip set. The project was a success with first-time working silicon. But Shahin Hedayat, vice president of engineering, said that "We certainly found that 0.25 micron and 0.35 micron are very, very different from the standpoint of the tool flow, especially when you talk about extraction and back-annotation."
Centillium did its own layout using Cadence Design Systems tools, and brought in 3-D extraction and analysis tools from Simplex Solutions (Sunnyvale). At 0.25 micron, Hedayat said, 3-D extraction of both capacitance and resistance is necessary; at 0.35 micron, in contrast, the resistance is not a concern.
Another new problem at 0.25 micron is power-grid analysis. If the power grid can't transfer power effectively, electromigration can result. Centillium used Simplex's "Thunder and Lightning" tool for clock-tree and power-grid analysis.
One of the biggest gaps Hedayat found is layout verification. "Designs are getting so large that older tools are coming to their knees," he said. "We need more hierarchical design-rule checking and LVS [layout vs. schematic]. We felt hierarchical tools are not ready for prime time, but we'll move to them in the future."
EDA vendors say that tremendous progress has been made with verification and physical design tools for chips with design planning, synthesis, at 0.25 micron and below. But putting it all together into a coherent methodology is the real challenge, said Jim Ensell, vice president of Cadence's deep-submicron business unit.
"While there is plenty of evidence about tools being sufficient to meet the needs of 0.25-micron design, there is also an apparent lack of awareness of the need for significant design methodology changes by the mainstream," he said. What's needed, said Ensell, is a shift to "smart verification" that leverages multiple levels of design abstraction and modeling, and "wire planning" that accounts for topological changes due to interconnect delays.
Raul Camposano, vice president of engineering at Synopsys Inc. (Mountain View, Calif.), also spoke of the
need for a new "mainstream" methodology for 0.25-micron design.
This methodology must couple logical and physical design more closely,
and make verification feasible for large designs by employing hardware/software co-simulation, formal verification, static timing and faster simulation.
Aki Fujimura, Simplex chief operating officer, noted that ASIC designers have traditionally avoided problems such as crosstalk or IR drop through conservative design rules. "At 0.25 micron, conservative design just isn't a good enough answer to problems any more," he said. "The amount you have to be conservative by is just too much to be practical."
Technical tool capability isn't enough, said Steve Pollock, director of marketing at Design Acceleration (San Jose). "Current ASIC design tools, libraries and design flows are capable for 0.25-micron designs," he said, "but the difficulty of their use limits their adoption to power users."
ASIC vendors ready
Several ASIC vendors are moving ahead aggressively on 0.25-micron design. The most successful, said Dataquest's Gary Smith, is IBM Microelectronics here. "We see a relatively rapid ramp-up for 0.25-micron technology into the mainstream area," said Poulin Shah, ASIC-product marketing manager at IBM.
Currently, said Shah, about 50 percent of IBM's ASIC designs are at 0.25 microns, and 10 to 15 percent are at 0.18 microns. Most densities are between 500,000 and 1 million gates. Shah said IBM is meeting its "yield objectives" but declined to elaborate.
At VLSI Technology (San Jose, Calif.), about 40 percent of ASIC design starts are at 0.25- or 0.20-micron technologies, said Tarek Ismail, director of product planning for corporate technology. "Defect density levels are not yet up to 0.35 microns, but it's normal and to be expected. We don't see any major issues with yield," he said.
On the design side, however, Ismail noted that customers are having difficulties with a number of issues such as IR drop on power busses, electromigration and crosstalk.
"Some new tools are attempting to address those issues, but in my opinion the maturity level is not there yet," he said.
Foundries at the ready
About 25 percent of ASIC starts at LSI Logic (Milpitas, Calif.) are at 0.25 microns, and this figure is expected to reach 65 to 75 percent one year from now, said Ronnie Vasishta, director of ASIC technical marketing. He said that 0.25-micron design needs better tools support in such areas as RTL design planning, power estimation and accurate parasitic extraction.
An increasing number of designers are doing their own layout, securing their own intellectual property and going to pure foundries such as TSMC. That company is currently fabricating about 10 percent of its chips in 0.25-micron technology, said Roger Fischer, director of marketing for TSMC USA. Yields at 0.25 micron are only about 10 percent under 0.35-micron yields, Fischer said.