DALLAS David Ditzel, president and chief executive of Transmeta Corp., kicked off the Micro-31 conference yesterday (Nov. 30) with a warning that the success of upcoming very-long-instruction-word (VLIW) processors will hinge on good physical implementations and on the availability of robust compilers.
Ditzel's pronouncements are closely followed because Transmeta (Santa Clara, Calif.) is widely assumed to be designing a VLIW processor. Such speculation has been fueled by a patent recently issued to the company which proposes a technique for speeding up RISC operations by decomposing instructions into VLIW-like parallel streams.
However, Ditzel pointedly steered clear of Transmeta in his speech and specifically declined to comment on his company's plans. "I would urge you not to read too much into that specific patent," Ditzel told EE Times. "It's indicative of just one tiny corner of what can be done."
In his speech, Ditzel told some 300 conference attendees that RISC may be reaching the end of its "learning curve" after 20 years of use. He noted that RISC, which originally began as a rebellion against complexity, has itself become bogged down by massive instruction sets and large die sizes.
"It was really fun in the early days; almost every computer company had a RISC chip," he said. "You did it because you could and you needed only a small design team."
Nowadays, that's no longer the case, Ditzel argued. "Today [in RISC] we have large design teams and long design cycles," he said. "The performance story is also much less clear now. The die sizes are no longer small. It just don't seem to make as much sense."
The result is the current crop of complex RISC chips. "Superscalar and out-of-order execution are the biggest problem areas that have impeded performance [leaps]," Ditzel said. "The MIPS R10,000 and HP PA-8000 seem much more complex to me than today's standard CISC architecture, which is the Pentium II. So where is the advantage of RISC, if the chips aren't as simple anymore?"
Moving forward, though, Ditzel hasn't sounded a death knell for RISC. Indeed, he sees good opportunities for the Sparc and Alpha architectures, particularly if Intel's upcoming Merced CPU takes time to gain widespread support.
As an architect, Ditzel cut his teeth designing a host of pacesetting microprocessors, starting with Bell Labs' Crisp. He is best known for his work as chief architect of Sun Microsystems' RISC-based Sparc family.
In his present role as head of Transmeta, Ditzel is seen in the industry as a proponent of VLIW. In his keynote here at Micro-31 (the conference is officially known as the 31st annual ACM/IEEE International Symposium on Microarchitecture), Ditzel noted that VLIW has been around for more than a decade and suffered commercial setbacks during its first attempts to find market success in the mid-1980s.
"Largely, VLIW has been a technique waiting for technology to catch up," Ditzel said.
That may be about to happen, propelled to prominence in the marketplace by Intel's IA-64 architecture. Perhaps steering clear of VLIW's previous market failures, Intel declines to tag IA-64 with that term. Instead, Intel has coined the moniker "Explicitly parallel instruction computing," or Epic.
Regardless, Ditzel believes that IA-64 and Merced may bring some great new VLIW-based architectural work into public view. At the same time, he warned that the expectations of the general public may be greater than can be delivered by a technology that's early in its learning curve.
Reiterating an insight made by other knowledgeable architects, Ditzel noted that VLIW relies on a balance between hardware and software. To deliver on its promise, cutting-edge compilers that can convert applications programs into parallel streams of executable instructions will be of paramount importance. These streams will feed the multiple function units on a VLIW or VLIW-like chip.
"As with the history of RISC chips, it will also take time for VLIW compiler technology to improve," Ditzel said. "I think management and users don't really appreciate how long this will take."
As for Transmeta's plans, which have remained veiled in secrecy, Ditzel did provide one hint about the company's possible design philosophy. He noted that Transmeta has a number of former MIPS architects in its employ. He also pointed out that, historically, the early MIPS R2000 processor contained simpler hardware but required more complex compiler technology than did its initial Sparc competitors. "Of course, once you've got the compilers, having simple hardware is better," he said.
Indeed, Ditzel sees simplicity as an overarching goal and complexity as the enemy of well-tempered microprocessor design. "One of the hardest things for designers to do is to leave things out," he said. "People always want to add features. Actually, it's the chief designer's job to keep things simple."