REDWOOD CITY, Calif. Claiming it is defining the design methodology for the system-on-a-chip era, Synopsys Inc. officially rolled out its long-awaited Chip Architect design planning tool here at an internationally broadcast press conference.
Aart de Geus, chairman and chief executive officer of Synopsys, said Chip Architect will do for system-on-a-chip design what Synopsys' ASIC synthesis tool did for deep-submicron design in the 1980s.
"In order to get to timing convergence, it is clear that we need a new design methodology," said de Geus. "Timing convergence has become the single biggest problem in design. What we are introducing is a timing backbone that links logical to physical design."
Chip Architect brings a combination of register transfer level floor planning, fast synthesis, global routing, and timing and power estimation to deep-submicron flows of 0.25-micron and below. It works at the black-box, RTL and gate levels.
Synopsys and its beta partners claim the tool gives users extremely accurate control of timing.
Tomohisa Shigematsu, vice president of Toshiba America Electronic Components Inc., said Toshiba used the tool on three actual designs from 170,000 gates to 1 million gates. The tool showed delay controlability with 5 percent of the design specification, he said.
Similarly, Marco Casale-Rossi, EDA partnership manager at STMicroelectronics, said Chip Architect had 7 percent less wire length on a block of 350,000 gates, half as many routing violations, and required 2.5 hours vs. 4.25 hours of routing time over the traditional Synopsys synthesis-to-Cadence place-and-route flow.