NEW YORK The proposed analog and mixed-signal testability bus standard, IEEE P1149.4, is out for ballot once again, but this time looks good for adoption.
P1149.4 remains a chip-level architecture, giving analog device pins 1149.1-style interconnect capabilities, as well as the more important continuous-signal stimulus and measurement capabilities necessary to test discrete components on a board that otherwise possesses poor physical access.
The architecture is controlled by 1149.1 protocols driving a test-access port which, in turn, manipulates the boundary register of P1149.4-compliant chips. New analog boundary modules at the boundary register's analog function pins allow the switching in of an analog stimulus and monitoring of the analog response in a random-access manner.
The stimulus and response signals are routed to two additional device pins, which can be bused to a system-level tester interface.
The final draft which incorporates fixes for issues that caused the spec to be voted down the first time it went to ballot, over a year ago will be submitted to the IEEE in time for its June REVCOM meeting.
Information about the spec and about the IEEE P1149.4 Mixed-Signal Test Bus Working Group is available online.