NASHUA, N.H. A tiny EDA startup will show its first two offerings a Verilog code reviewer and a Java-based Verilog analyzer at the International HDL '99 conference next week in Santa Clara, Calif.
The startup currently has a staff of one. Sashi Obilisetty, the company's chief executive officer, is a former contract tool developer who began developing Verilog and VHDL tools for Alternative System Concepts (Windham, N.H.) and later for Cadence and Viewlogic.
In her latest venture, a self-funded company called DualSoft LLC, Obilisetty has created two products. DualSoft's ReviewVer is an automatic Verilog design-code reviewer targeting design and IP houses, while Jades is a Verilog analyzer developed in Java and targeting EDA companies interested in a Java-based front end for new simulation or synthesis tools.
According to Obilisetty, ReviewVer is a code reviewer that can be used to implement and enforce a company-wide coding policy for Verilog designs.
She said the tool is different from competing tools in that it is fully tool-flow-independent and customizable.
"Engineers come and go from companies," said Obilisetty. "This tool ensures that your new designers as well as your old designers conform to your particular Verilog coding guidelines."
Obilisetty said design guidelines can be defined in coding, style and documentation areas.
The tool lets users write Verilog constructs and specify things like the number of ports. In terms of style, the tool allows users to define such things as line length and naming conventions, which ultimately eases translation to VHDL. Users can also specify the level of detail of documentation they would like for the various constructs in Verilog.
She envisions the tool being used by IP houses as well as by large companies to enforce their own design-for-reuse guidelines, while others may use it for their customized flows.
"IP providers can use this tool to structure the way their engineers design IP," said Obilisetty. "For instance, if they write in Verilog, they can enforce some rules so that the tool can be easily translated to VHDL with a standard translator."
The tool can be used on Verilog input files and linked to graphical-entry tools; it outputs a list of rule violations by coding, style and documentation.
ReviewVer runs on all Java-compatible platforms and starts at $7,500. DualSoft's second offering, Jades, is slated for release in May. Obilisetty said the tool is a Verilog analyzer that EDA companies can use for next-generation Verilog simulation or synthesis front ends.
"Java will become the language of choice for most EDA developers because it is very easy to work with," said Obilisetty. "This front end will allow EDA companies to get a jump on the competition in Java-based tool development and re-engineering."
Obilisetty said she plans to open an R&D branch in India.
Obilisetty will present a paper on IP authoring on April 7 at the International HDL Conference.