System-on-a-chip (SOC) technology is usually associated with the merging of digital circuits in the form of predesigned intellectual property (IP) blocks. But analog/mixed-signal (AMS) IP often has a critical system role to play even in ostensibly digital designs.
The nature of analog circuit design makes reusable IP a somewhat different issue than in the digital case. A generally accepted implication of IP is that it is reusable. Today, AMS IP can only be found in "hard" or layout form. However, this does not imply that it cannot be reused. IP providers design in such a way that blocks can be rapidly and reliably re-targeted.
If the "system" is a state-of-the-art high-performance, high-frequency custom mixed-signal IC such as a partial-response, maximum-likelihood (PRML) disk-drive IC or a single-chip radio, AMS IP will naturally be required. However, the need for AMS IP extends into the realm of the "digital" SOC, too.
Those SOCs are programmable general-purpose systems that have at least one processor or controller core. They integrate many functions of the end product, include hardware, software and peripherals, and typically use bus-based communications between the blocks. In addition, their application is targeted at the consumer market, where the SOC designer is being measured on a time-to-market basis.
Those consumer devices require real-world interfaces. Low cost and feature-set requirements therefore drive the AMS functionality onto a single chip. Typical IP blocks that have been integrated include audio-range data converters and video digital-to-analog converters for the red, green and blue video signals. In addition, there are physical layers for high-speed wired communications, and phase-locked loops for both system and video clock synthesis. In fact, for many applications, SOCs will actually be analog-in and analog-out. For example, a video-on-demand SOC may have an MPEG stream enter on an Ethernet physical layer, where it is then decoded internally and sent out via the video D/As to the screen.
It is true that the majority of the circuitry on the chip is digital, and from a system-verification point of view, looking at the chip from the inside out, the SOC is digital. However, from the outside, the digital circuitry is only an implementation detail. And from a manufacturing-test point of view, the chip is truly mixed-signal, where both analog and digital must be tested.
At the same time, market drivers will also force some AMS components off-chip. For example, AMS functions for new wireless standards such as wideband-CDMA are unlikely to be integrated into "digital" SOCs in the near future. There is no doubt that over time more and more AMS functions will be integrated, but today the emphasis is on the lower-performance components that can be designed for robustness and reuse.
Once a choice has been made as to which analog functions should be integrated, the difficult question becomes how AMS IP can be designed to operate correctly in a system-on-chip. First, the design team begins with a front-end acceptance step, the mechanism by which a design is accepted.
In this phase designers account for the risk, cost and schedule factors that will determine the manufacturability of the chip.
The next step is system codesign. Given a functional model, this step partitions and maps the design to hardware and software components based on an IP database or on a better-qualified set of IP found in an application-specific integration platform. Hardware design is performed via a hierarchical block-based methodology. Care must be taken to plan the chip with respect to clock, bus, test, power and timing architectures.
New blocks are authored and legacy and third-party IP blocks are "collared" to add suitable interfaces for the SOC. Embedded software design follows a similar methodology. Throughout the core-design process, a complex verification methodology balances many technologies, including hardware/software coverification, formal-property and equivalence checking, static timing, and cycle-, event- and mixed-signal-based simulation to ensure an adequate level of verification coverage.
Virtual test is also accomplished as part of the core methodology to bring in test-program development time. Support functions include a rapid prototyping environment for applications requiring real-time data streaming for verification.
Design for manufacturing test (DFT) is critical to the hardware design of the blocks. The isolated nature of the IP blocks, the inclusion of AMS blocks and the number of input/output pins associated with each block makes access to all of the IP from a tester virtually impossible. To design for correctness throughout the design sequence, proper use of the methodology is essential. Process monitoring by using key metrics is necessary, along with constraint management and the use of an experience base for design-knowledge reuse.
At the heart of mixed-signal SOC design is AMS block design. This process is similar to the design practice used for AMS custom ICs. Specifications are mapped to a behavioral model where parameters are chosen for the basic building blocks. Those parameters become constraints to schematic block design. The schematic is then mapped to layout or physical design.
Some amount of automation can be applied but, in general, the process is a custom, design-intensive effort based on best practices. Verification is used in all phases of the design, from behavioral simulation to design-rule checking.
The key difference when crafting SOCs is that the design is targeted for a leading-edge digital process-0.35 to 0.18 micron.
The process has only one layer of polysilicon, requires a low supply voltage and has little consideration for AMS design. Such limitations exacerbate design for robustness both in terms of substrate coupling from the noisy digital circuits as well as process variability.
The trade-off, however, is that design performance requirements will be lower to allow for integration. It is for those reasons that design for reuse is made easier. The less process-specific nature of the design in conjunction with the use of systematic top-down design methodologies makes automation tools easier to implement.
After the block has been designed, it must be packaged to allow for rapid integration. One aspect of this is that all IP blocks including AMS should be delivered in a similar manner. For example, if two IP providers deliver information in two different formats, the SOC designer is faced with translating the information. This opens the risk of translation errors.
A solution is provided by the Virtual Socket Interface (VSI) Alliance, which defines a comprehensive set of standard deliverables for IP for both digital and AMS blocks. The mixed-signal development working group in the VSIA is specifying the models required to support typical SOC integration and verification flows.
A similar set has been developed for digital IP. While the VSI focuses on the technical aspects of IP exchange, an IP provider also needs to consider a delivery plan, application engineering support and IP business issues that range from pricing to patent indemnification.
AMS IP now exists. SOCs require it, and by using the proper design techniques and methodologies, those blocks can be integrated successfully. SOCs with reused AMS IP are being designed today, and as process technologies improve, AMS IP will see continued use in the future.
Chang is also chairman of the VSIA's analog/mixed-signal development working group.