System-on-chip designs offer many advantages. However, they also place a much greater burden on the IC manufacturing process because SOC brings board-level integration problems down to the chip level. That means that those concerns-power dissipation, design reuse, hardware/software codesign, design-for-test (DFT) and design for manufacturability (DFM)-must now be dealt with on the chip. Moreover, other integration challenges, normally associated with system-level design, are encountered. Among them are intellectual-property reuse, process compensation, power-rail noise, crosstalk noise and delay-prediction problems.
However, there is another hurdle: successful SOC design requires that the level of integration be cost-effective at the start and that there must be a technology-migration, cost-reduction strategy. Often, little thought was given to such migrations-for example, an analog process done later in smaller geometries may require compromises. Or external IP cores may not be available for new generations.
Today, the difference lies in the reduced cycles required for ever-shrinking time-to-market. Product cycles used to last five to 10 years, and the project could support a large design team with many specialists. There was a tendency to work on just one specific architecture-for example, IBM-compatible mainframes. But now, with long design cycles and large team efforts neither cost-effective nor practical it is not unusual for teams to face cycles measured in months, and occasionally even weeks.
For these reasons, SOC requires design reuse as well as hardware and software codesign. At Fujitsu, we leverage this expertise through our IPware program. This program contains the "IP Bank," a repository of IP specified by the Virtual Socket Interface Alliance (VSIA), as well as the "IP Highway," an Internet technology-based IP-sharing infrastructure. Using the IPware program ensures that designs generated anywhere in the company can be reused across the board and around the world. The concept is derived from the current VSIA working group, with the addition of internal formats to guarantee that custom tool flows can be supported properly.
By keeping track of the VSIA standard, we ensure ease of industrywide IP reusability, while keeping up with internally set standards that allow significant improvements over the industry standards. Also, for IP-based design it is critical to be sure that a complete flow exists not just for the layout-synthesis process, but also for DFT and DFM. We are achieving this by using built-in-self-test (BIST) techniques to deal with the complexity of test and production turnaround times.
Since product cycles are so short (sometimes even nine months) the need for a smooth manufacturing process becomes essential. Ignore this and be overwhelmed by the turnaround requirements and the need to do quick failure analysis if something goes wrong. It is essential to have a program that yields DFT as well as a smooth transition between design and production. Internet-based technologies should be deployed to guarantee trackability of design and quick resolution of manufacturing problems.
For example, a typical SOC design might integrate a processor, a graphics accelerator, some memory and another peripheral core. Such a single-chip device would include significant IP from outside sources and contain mixed process technologies. The vendor can differentiate the product by achieving a new price point, a new performance level and excellent time-to-market.
And, like large-system design, SOC design requires significant specialization including related costs, which most design houses do not want to incur. Furthermore, especially in the United States, there is a shortage of qualified individuals to address the complexity concerns involved with SOC design.
This has led to the creation of "design methodologists," a new position that allows ASIC-semiconductor houses to minimize their overhead by increasing the number of designs each methodologist can support. Such people are also found in vertical design houses, such as Fujitsu, IBM, Intel and Sun Microsystems, reflecting the need to meet aggressive time-to-market schedules.
We have been able to generate the methodology infrastructure by allowing for the specialization of designers. In addition, intranet facilities are used for design implementation and information-sharing among teams in different places. Thus, we share knowledge and design expertise globally.
At Fujitsu, the methodologist ensures a clear path for technology migration and cost reduction. Verification of flow using a heterogeneous tool environment, dealing with a wide range of related matters such as delay prediction and IP porting are among the methodologist's responsibilities. While traditional design teams are familiar with this responsibility, it is new at the SOC level.
The methodologist also makes certain that not only do current designs encounter a smooth production flow, but also that the process for scaling design capability is in place. This requires an investment in infrastructure and close cooperation among process R&D, internal CAD organizations, independent software vendors and design engineering and production disciplines.
Global organization requires sophisticated communications and development environments between the region and corporate headquarters. Since regional teams assume complete responsibility for their own support, each site has a cache of knowledge for all aspects of the design flow. Thus, regions can deal with local customer concerns at the local level without incurring the time penalty of corporate overhead. Once the methodology is well-defined at the regional level, a transfer to the corporate infrastructure takes place for global benefit.
We find that all this development work facilitates dealing with complex SOC design topics. The ideal is a well-balanced approach to methodology-flow-tool development, with the capability to provide timing constraints from synthesis through the place-and-route tools. And this allows for a tight timing closure loop.
Meanwhile, it is also essential to provide hierarchical partitioning of large designs to ensure scalability of the layout process. Formal verification is used for dealing with simulation bottlenecks, and internal tools are used for verification of the power grid. Most problems related to SOC can be handled with ease if preparation and verification are addressed early.
Basically, SOC design requires the integration of disparate technologies and subsystems in a short time. This is accomplished by achieving compatibility among logic, RAM and analog design. Currently, most of the effort deals with making RAM and logic processes compatible, though this necessitates compromises among speed, leakage and power dissipation.
The primary reason is that the production line today must be as generic as possible to limit the cost of specialized equipment. In the future expect production lines to be more flexible for dealing with scale integration. Also, we expect to see enhanced performance in specific products so that, for example, a line producing DRAMs can be reconfigured to produce processors. This will lead to better use of fab capacity and better performance and integration of SOC devices.
The bottleneck will be how quickly the production line can be reconfigured to support this mixed process.
Furthermore, the tools will have to be updated to deal with any new uncertainties in this fab configuration. Tools will no longer have a fixed process window but a sliding one with associated costs for each one. For instance, this might mean mixing the bipolar and CMOS processes with flash and true 5-V ones.
In such a case, the synthesis tools will have to be fully aware of the process capabilities. Partitioning tools that allow for system reconfiguration will be needed as will system tools that allow cost modeling based on total system cost. So proper trade-offs can be made within small market windows. And, embedding test within the device will allow for more-robust qualification. Coupling this with a diagnostic ability will bring up systems faster. Testers may then be assigned to deal with difficult issues like D/A and A/D converter linearity, PLL performance and analog tests.
The current register-transfer level (RTL) of abstraction and the trend toward C-based or system-level abstraction will pave the way for some form of object-based abstraction. In this way, concurrent logical processes will be encapsulated coincident with physical objects. Thus, an optimum price/performance point will be achieved not just by hardware implementation but by the needs of the product.
SOC design is an excellent way to achieve new price points, performance targets and integration targets. It does, however, require a good infrastructure.