AUSTIN, Texas Another network-processor startup has tossed its hat into the ring, with a novel pattern-matching architecture that eases the high-layer packet analysis that will be necessary to alleviate router bottlenecks in public backbones. Agere Inc. is one of many specialized processor companies moving into the realm of application-aware switching.
The 35 employees at the small Texas startup are developing an architecture that requires the Fast Pattern Processor (FPP), heart of the search algorithms, to be delivered before a route-switch processor (RSP), the initiation point of most network-processor startups.
Vice president of marketing Bob Bridge said that, since Agere considers OC-48 (2.5-Gbit/second) speeds to be the heart of its design space, intelligent reduction of route-table space took precedence over mere packet-header analysis. Agere wants to handle OC-192 (10-Gbit/s) speeds in standard CMOS architectures, he said.
First-draft startups, meanwhile, including MMC Networks Inc. (Sunnyvale, Calif.), Xaqti Corp. (San Jose, Calif.) and Softcom Microsystems Inc. (Fremont, Calif.), are expanding beyond Layer 2/3 switch-routing to probe beyond headers, into packet payload content itself.
Jeremey Donovan, an industry analyst at Dataquest Inc., said that several ideas for parsing high-layer packet-analysis problems hold merit, and that differences among them may lie more in marketing than in technology. He also believes the growing field of startups may face a rapid consolidation.
"We don't expect any of the 10 or so network-processor companies to remain independent companies to the point of an initial public offering," Donovan said. "We're increasingly holding the view that the networking semiconductor industry will consolidate in the same way the networking systems industry has in recent months."
But that isn't stopping the newcomers from making some important architectural claims. Agere, with roots in pattern searches and neural-network list processing, said its pattern-matching approach is designed to work with any protocol stack, no matter how the data payload may be encapsulated. Bridge insists a reduction of pattern-matching search space is critical for handling multigigabit packet analysis at wire speed.
The company began in the work of Vic Bennett, a cofounder of Coral Networks Inc., who formed a list-searching startup called Nodel Corp. in 1995 and developed his technology in multiple FPGAs by 1998. Two Austin ventures provided seed financing in mid-1998, at which time Ford Tamer joined as chief executive and Eric Rothfus, of Tivoli Systems Inc., became chief technology officer. The goal was to turn Bennett's subsystem concepts into partitioned network-processing deliverables.
"It's one thing to say you can look at some class-of-service bits at OC-48. That's not the issue," Bridge said. "Can you use a 100-MHz core to perform hard tasks at OC-48, such as processing access-control lists? That's where we think our architecture will have an edge."
The combination of FPP and RSP chips is designed to be used either right on a line card, touching the physical channel directly, or on a shared-resource controller card in a router or broadband switch. List-parsing on the front end will allow Agere to move into quality-of-service packet prioritization, traffic engineering and Internet Protocol tunneling functions such as virtual private networks and network address translation, even for 10-Gbit networks.
The gating factor, Bridge said, becomes finding memory that's able to keep up with the processor. Motorola Inc.'s announcement of 333-MHz copper-based SRAMs may provide Agere with the last piece of its OC-192 portfolio, he said.
The company claims to use as much internal parallelism and pipelining as two other startups, C-Port Inc. and SiTera Inc., but says that using pattern matching to reduce table lookups makes for a more effective use of internal parallelism. Agere has yet to provide full details of its internal architecture. However, unlike large, smart content-addressable memories (CAMs), the Agere FPP can handle millions, not thousands, of patterns, and processes patterns of any arbitrary length.
While Agere's development system does not use C-like constructs, its PayloadPlus application-development code is similar to a protocol-definition language, with route-table search information embedded automatically into the code. This allows fast development of optimized code for new protocols, the company said.
Agere is offering FPP versions for OC-12 lines in the second quarter and OC-48 versions in the third. The RSP, handling packet queuing and prioritization as well as traffic shaping, is due in an OC-3 version in the third quarter, in an OC-12 version at the end of the year and in an OC-48 version in early 2000. As enhanced functionality becomes viable in dedicated silicon, Agere will develop specialized coprocessors for higher-layer tasks.
To MMC Networks, which originated many concepts for high-layer packet analysis in its AnyFlow family, the new activity validates the functions defined in its 5400 and 5500 architectures. Chief executive officer Doug Spreng said that MMC's decision to develop traffic-shaping processors optimized in assembly-level instruction sets has been upheld by the new interest in highly optimized engines.
The onslaught of startups is helping to show MMC where additional traffic-engineering instructions may have to be added to the AnyFlow instruction set, said MMC's director of marketing, John Kennedy. MMC also is looking at the use of higher-layer programming languages for traffic-shaping constructs.
Softcom, which unwrapped its GigaBlade architecture last July, has advocated keeping header-analysis processing functions generic, implemented in state machines, while keeping specific tasks downloadable in an external BIOS. At the New World Service Provider conference in Denver in late March, Softcom unveiled its Power Provisioning Processor family, the first chip-level instantiation of what the company had demonstrated in GigaBlade.
Softcom said its state machines handle three basic tasks: identification of packets requiring special handling; provisioning traffic based on predefined rules; and counting the relevant statistics for packet classification. This requires analysis as deep as 64 bytes, according to Softcom president Tony Stelliga. The Softcom Engine processor is given its networking assignments through a high-level application programming interface the company calls BladeRunner.
At Xaqti, the GigaPower and ActiveFlow processor architectures that define high-layer packet provisioning are being structured with a set of specific engines that operate in parallel, said vice president of marketing Samba Murthy. These include dedicated processors for remote monitoring and for IP differentiated services (Diff Serv), which are to be launched later this year. Other traffic-shaping engines are under development, he said.
Murthy said that software models and emulation engines will be offered to key customers prior to each specialized processor being committed to silicon.
Xaqti also is trying to open out lower layers of the Open Systems Interconnect software stack via the CSIX open switching coalition it formed with physical-layer switching vendor Power X Ltd. Murthy said an announcement is imminent-perhaps this week-about additional CSIX members, including many network-processor companies that are compete with one another.