SAN JOSE, Calif. Launching what appears to be the strongest private attempt in years to create a new high-level design language, Co-Design Automation Inc. will announce its Superlog language this week. The system-level language combines the best features of Verilog and C/C++ while allowing interfaces and translations to and from C/C++, Verilog and VHDL, the company said.
Drawing on the expertise of industry luminaries such as Peter Flake, a creator of the Hilo simulator, and Phil Moorby, creator of the Verilog language and simulator, Co-Design aims to simplify high-level design with a language that will support more capable tools and a more cohesive design flow than currently available.
Co-Design (San Jose, Calif.) plans to introduce Superlog-based EDA software tools for systems-on-chip designs early in 2000. Other EDA companies already working with Co-Design may also announce Superlog tools around the same time.
"We now have what we think is a world-beating language that can support specification, logical design, implementation and verification," said Simon Davidmann, chief executive officer of the startup, which has offices here and in the United Kingdom.
But Co-Design could find itself at odds with some industry observers who believe that as engineers turn to software programming languages (such as C/C++ and Java), as well to VHDL and Verilog extensions and to proprietary and domain-specific languages, yet another design language is unlikely to achieve success. Indeed, the industrywide System-Level Design Language (SLDL) effort, which is being coordinated by a VHDL International committee, is arguing for a semantic framework that bridges multiple languages, rather than for a single, system-level design language. The SLDL committee plans to unveil the framework, called Rosetta, at the Design Automation Conference in June.
Davidmann stressed that Co-Design will not try to displace established EDA tools at the back end of the design process. "The front end is its scope, with synthesizable VHDL and Verilog as outputs from Superlog tools," he said. He added Superlog is relevant both before and after systems are partitioned between hardware and software.
Co-Design's business plan calls for putting Superlog in the public domain to encourage third-party development. "It has to become free for other companies to utilize it," said Davidmann. "But it also has to be closely controlled and not committee-driven." He declined to reveal details of forthcoming tools or the names of EDA partners said to be working on Superlog-based offerings.
David Kelf, appointed last week as vice president of marketing at Co-Design, said a new design language has to speed and unify the design process while providing "an evolutionary path [from existing tools and legacy code] for hardware engineers, system architects and software engineers."
In Gateway's image
Co-Design's strategy essentially seeks to recreate at the system level the success of Gateway Design Automation Inc., which introduced Verilog as the proprietary modeling language for Verilog simulators in 1986. If Co-Design Automation follows that precedent, it can be expected to offer at least a simulator and possibly architectural synthesis tools as well.
"Verilog HDL was a breakthrough for the hardware design community in 1986," said Davidmann, but "over the years the basic methodology has been augmented with various utilities, to the point where the total flow is now an absolute mess. A design language targeted to the exact needs of system-on-chip designers is required. That is the challenge that we are fulfilling."
Co-Design was founded in 1997 by Davidmann and Flake. Both began their careers under Prof. Gerry Musgrave at Brunel University (Uxbridge, England) and worked on the Hilo simulator, the first commercial HDL-based simulation system.
Flake, chief technology officer at Co-Design and architect of the Superlog language, was the language architect and project leader of the Hilo development program while at Brunel and subsequently at GenRad, which took over commercial sales of Hilo. Davidmann's recent experience has included leading the European operations of Ambit Design Systems and Virtual Chips.
While developing Superlog, Davidmann and Flake have also sought the input of a technical advisory board that includes respected design-language experts. In addition to Moorby, they include Don Thomas, a professor at Carnegie Mellon University, and Mike McNamara, a developer of Chronologic's VCS simulator and now chief executive officer of SureFire Verification Inc. (Campbell, Calif.).
"I think there's a need to capture more of the design intent, and these folks [Co-Design] are taking an interesting approach to it," said McNamara. He said SureFire has not entered a formal agreement with Co-Design but is "actively following the language and the direction."
So far Co-Design has been backed by private investors rather than venture-capital money. Investors include Andy Bechtolsheim, a cofounder of Sun Microsystems Inc. and now vice president of the gigabit switching group at Cisco Systems Inc. (San Jose); Venk Shukla, a vice president of Ambit Design Systems and now chief executive officer of WebByPhone Inc.; and Rajeev Madhavan, founder of Ambit and now chief executive officer of Magma Design Automation Inc. (Cupertino, Calif.).
Magma recently introduced an integrated physical design system called Blast Fusion, and Madhavan said the company will work to ensure that Blast Fusion can read in Superlog and take it all the way to GDSII layout files.
Gary Smith, principal EDA analyst at Dataquest Inc., said that Co-Design has a fair chance of establishing its language. "The Verilog guys are saying they've run out of steam," said Smith. "The VHDL guys are pretty much saying VHDL is dead. C++ isn't going to work at all, and the C guys can't come up with a solution unless they really restrict the problem."
Dennis Brophy, chairman of Open Verilog International (OVI) and director of strategic business development at Model Technology Inc., agreed with the need for a new language. "The technology for RTL, as we understand it, has limits when you do architectural exploration." Needed is a language that lets users think in terms of "transactions" rather than absolute units of time, Brophy said.
He said Co-Design is among the companies that have made presentations to OVI's architectural subcommittee and that it posited Superlog as an OVI candidate standard. While no decision has been made, Brophy said he is "keenly impressed" with Co-Design's idea of pulling together the best aspects of existing languages.
Superlog retains most of the features of Verilog and VHDL, including support for hierarchy, events, timing, concurrency and multivalued logic. It also borrows useful features familiar from software-programming languages such as C and Java, including support for dynamic processes, recursion, arrays and pointers. It includes support for communicating processes with interfaces, protocol definition, state machines and queuing.
A major strength of Superlog is its ability to define interfaces, said McNamara. "You figure out the bus, and then all the readers and writers of the bus fall out from the definition of the bus. With previous HDLs, you describe the action of devices that sit on the bus each one separately without really thinking about the interface itself."
"Peter Flake has also done a great job at including features that will be useful for tool building," said Davidmann. "He's looked at making sure Superlog can handle formal verification and at the ability to include attributes and constraints for constraint-driven design elaboration. A lot of functionality can be described in a small amount of code."
Davidmann estimated that Superlog will need one-half to one third the number of lines of code to describe a function as Verilog at the same abstraction level, adding that Superlog can go much higher in abstraction.
Co-Design's claims of a productivity boost lie both in the language itself and in the easing of interfaces between domain-specific tools. Kelf, formerly director of marketing for simulation and verification products at Cadence Design Systems Inc. (San Jose), noted that "disparate pieces of the overall flow now need different languages and extensions. The standard solution for major tools has been the PLI [programming language interface] as a bolt-on addition, but [that] slows tools down. It can bring a simulator to its knees."
Kelf argued that having a single language will allow tools to continue to work at full speed. It should also cut out the enormous burden of format-translation routines that currently have to be written to make different EDA tools work together.
It remains to be seen whether Superlog will emerge as a competitor or a complement to the efforts of the SLDL committee, which is already questioning the premise behind the startup's approach. "Several years of workshop results have proven that it's neither technically feasible nor necessarily desirable for one language to try to do everything needed at the system-on-chip level," said Steve Schulz, president of VHDL International and executive sponsor of the SLDL committee. That's particularly true when one begins considering such issues as analog and mixed-signal design, he said.
While cautioning that he is not specifically familiar with Superlog, Schulz said SLDL's philosophy is to work with any languages out there, including any feasible newcomers.
Davidmann's pitch for Superlog may strike a chord with those who believe the best standards are those created by industry use. "Looking at history, we've seen that one language usually wins. We will have much cleaner design flow based around Superlog than you could ever have with multiple languages," he said.
He added that engineers who turn to C or C++ rarely use the language as originally defined but add private extensions or introduce special classes.
Moorby similarly observed that "design problems have generated the need for language extensions for example, architectural specification, functional testing and hardware-software codesign. Forcing extensions to one language, such as C, to meet these requirements only adds to the complexity of the methodology.
"Superlog . . . utilizes the power of C with the simplicity of Verilog to provide the right balance for productive design."