In the past, to get the kind of application-specificity we needed in our embedded systems, many of our previous designs involved placing a microcontroller and some form of programmable logic-FPGA or CPLD-both on the same board. Ideally, we could have created our own system-on-chip design if we had the production volumes and development budget to justify such an endeavor.
However, an alternative, Triscend Corp.'s (Mountain, View, Calif.) E5 configurable processor, came to market just in time to provide us with the integration levels of a SoC design but with the programmability of FPGAs and CPLDs. The E5 configurable processor contains an 8051/8052 binary compatible, 10 MIPS, eight-bit 8032 microcontroller with 8 to 64 kbytes of RAM and 315 I/O pins, as well as between 5,000 and 40,000 gates of programmable logic. An internal configurable-system-interconnect bus (CSI) links the processor and other peripheral blocks on-chip through a socket that provides 32 address lines, eight read and eight write data lines, wait-state control, DMA control and breakpoint control.
The application in which we first used the E5 was one that required a serial peripheral interface (SPI) so that we could communicate with other on-board memories plus serial A/D and D/A converters. SPI is a four-wire interface that connects a master device to a slave device via a serial connection. To minimize communication delays, we wanted the SPI to operate at least up to 4 MHz. Because SPI is commonly associated with Motorola microcontrollers, it is often difficult to find SPI embedded in Intel-based architectures like the 8032. Designers often create an SPI on the 8032, either using its integrated UART or by bit-banging values to a serial port. Both traditional options were too slow for our application. We could also choose to build our application with an 8051 microcontroller and companion programmable-logic device. However, the E5 configurable processor offers lower power consumption and lower EMI due to its single-chip integration.
The E5 configurable processor also provided us with options on how we want to transfer data to and from memory through the SPI. As in traditional 8032 design, we can poll the SPI's status register to monitor when data is available. Or we could have the SPI interrupt the 8032 whenever data is ready. In both cases, the 8032 wastes bandwidth moving the data from the SPI to somewhere in memory.
The E5 provides a two-channel direct-memory-access (DMA) controller and functions within the programmable logic can request DMA transfers. Instead of interrupting the microcontroller, the SPI could request a DMA transfer whenever data is available. The DMA then grabs the data from the SPI's data register and stores it in on-chip RAM. All this is accomplished without disturbing the 8032's program flow, giving the processor even more available bandwidth.
Designing the interface in programmable logic was different from writing a subroutine to perform the same function. Usually, most "soft" peripherals are coded using "C" or assembly language. However, configurable processors require some proficiency with logic design tools like schematic capture or logic synthesis. Triscend presently supports OrCAD schematic capture and VHDL or Verilog synthesis using FPGA Express, version 3.1 from Synopsys. We opted for schematic entry at the time because it was the only method available.
Most of the logic entry is similar to most any other digital technology. The Triscend library contains gates, flip-flops, memories, etc. However, a few unique symbols provide connections to the internal CSI bus socket. For example, one symbol connects to the data write bus, another to the data read bus, and still others to the address bus. Some special symbols, called selectors, provide address-decoding functions. By attaching other symbols to the selector symbols, it is possible to decode anywhere from a single byte to a 4G region in memory. Moreover, the decoded access can be further qualified for the 8032's external data space (XDATA), code space or even to one of the 8032's special function registers (SFRs).
Using the OrCAD Express simulator, one can simulate logic design, including transfers over the CSI bus. However, the simulation model does not run 8032 assembly code so we modeled the bus transactions in a simulation file.
'Soft' module library
After entering and simulating the design, we created an EDIF 2 0 0 net-list to be imported into Triscend FastChip development software, which allowed our designers to specify the entire design using a built-in "soft" module library containing commonly used peripherals for microcontroller designs. Unfortunately, the SPI core was not available when we started our design. Designs like ours can also be imported from EDIF. Likewise, FastChip communicates to third-party microcontroller development tools. Fast-Chip creates a header file with address locations plus initialization routines for some of the "soft" module functions. FastChip also reads object code from the assembler or compiler and combines it with the data file used to program the logic on the configurable processor.
After importing the EDIF file, and using FastChip to create a graphical module, the integrated I/O editor allowed us to assign I/O pins to the SPI connections on our development board. After defining the hardware design, we ran a function in FastChip called "Bind" which essentially maps our logic description to resources available within the on-chip programmable logic. The complete SPI interface required only 37 configurable system-logic (CSL) cells out of the 512 available on the smallest Triscend E5 device.
Using less than 7 percent of the device resources, we were able to meet our data-communication objectives for the SPI interface without having to burden the 8032 microcontroller.
Although our final target is the 512-cell TE505 configurable processor, we used the 2,048-cell TE520 processor because the TE505is not slated to be available until the end of the year. However, all four Triscend configurable processors are pin-compatible in the 208-pin plastic quad flat pack. That will allow us to develop and deliver prototypes quickly.
At this point in the process, the hardware design was practically complete but we still needed to write software. We used the recommended Keil 8032 assembler to create the application software for this design. Our assembly code referenced the header file created by the FastChip "Generate" program using an $INCLUDE statement.
Next, we called a subroutine-also created by the Generate program-that initialized our "soft" peripherals.
The rest of the software development proceeded like most any 8032 microcontroller design.
Because the Triscend E5 is binary-compatible with the 8051/ 8052, we were able to use Keil's instruction-set simulator to verify correct program operation, though not all functions are implemented in the Triscend E5. The logic-only functions require the OrCAD simulator.
After verifying the software, we assembled and linked the code to create an object file. Back in the FastChip software we integrated the assembled code with the data file created by FastChip's "Bind" program. The result is an 8051-compatible program/data file used to initialize the SRAM-based configurable processor at power-up.
When power is first applied, the configurable processor boots from external byte-wide PROM, loads its initialization data into the on-chip programmable logic and begins executing code from the external PROM. We used a 256k x 8 flash memory for our application and the on-chip memory interface unit provided a glueless interface.
To conserve I/O pins, one can use an external serial PROM to hold the initialization file, though application code must be loaded into internal SRAM before executing the code.
For fast development, it is possible to download the initialization file directly into the device via a JTAG cable connected to your PC's parallel port.