WILSONVILLE, Ore. Claiming a major step forward for design reuse, Mentor Graphics Corp. rolled out its QuickUse Development System at the Design Automation Conference (DAC) on Tuesday (June 22). By providing an infrastructure that automates many aspects of intellectual-property (IP) selection, integration, verification and implementation, QuickUse is claimed to have reduced design times at Toshiba Corp., its first customer, from months to days.
Based largely on Mentor's FlowXpert tool, QuickUse is a tool-independent, platform-independent system that guides users from system specification to GDSII layout files. It provides an IP repository, "socketization" and certification of IP blocks, electronic chip specification, automated chip integration, and support for verification and physical design.
"This is our most significant announcement in recent times," said Wally Rhines, president and chief executive officer of Mentor Graphics (Wilsonville, Ore.). "We are announcing a standard-product infrastructure with a proven capability to do real designs from specs to tape-out. This suddenly takes design reuse into a new realm."
Gary Smith, chief EDA analyst at Dataquest Inc. (San Jose, Calif.), said he believes QuickUse may prove to be the most important announcement at DAC. "This is going to give large OEMs a solid methodology for core-based design," Smith said. "With this, you can really do system-level integration."
QuickUse requires a lot of customization and comes only with Mentor consulting services. It's targeted at large semiconductor and systems houses involved in IP creation and integration.
Toshiba used QuickUse to implement its company-wide Smart Design Initiative (SDI). Pilot designs using the 900L1 and TX19 microprocessor families reportedly went from chip specification to tape-out in five days with QuickUse.
Although QuickUse itself has various automated capabilities, it doesn't include design creation or implementation tools. It can be customized to any tool flow and requires no specific Mentor point tools. Phil Bishop, vice president of worldwide consulting at Mentor, said the design flow used by Toshiba included tools from all four of the world's largest EDA vendors: Cadence, Mentor, Synopsys and Avant!
At the core of QuickUse is a Web-enabled IP repository, built around an Oracle Corp. database. Once IP is stored in the repository, designers can search and select IP from an online catalog and can store and retrieve design-reuse deliverables. The repository provides such features as version control, configuration management and security.
"All of the IP that goes into the system has to be socketized," noted Jeff Jussel, director of strategic marketing and consulting at Mentor. "Socketization defines certain interfaces, like bus data, interrupts, memory control and logic. When IP is chosen, like interfaces are automatically connected in the system."
IP must also pass a qualification process that checks for the existence and proper formatting of deliverables, good register-transfer level (RTL) coding styles, sufficient functional-test coverage and completeness of documentation. That provision upholds standards spelled out by the Reuse Methodology Manual and the Virtual Socket Interface alliance.
The Web-based user interface provides instant access to IP blocks and related information. QuickUse employs Java "servlets" to allow the system to respond dynamically to data.
The system provides a graphical user interface that lets users describe such specifications as interblock connections, voltage and I/Os, and it can automatically generate design data, tool scripts and verification suites based on the specification data.
The socketization and specification information helps automate chip integration. With I/O information, QuickUse can automatically hook up the pad ring. And by taking in testbenches for individual IP blocks, QuickUse can generate a set of top-level test vectors for verifying the entire chip.
The socketization information lets QuickUse connect IP in system-on-chip designs. If a block drives a particular interface and another block is driven by that interface, QuickUse can make a socket connection. That will help avoid the need for manual pin-to-pin connections.
While QuickUse does not by itself run verification or physical design, it can generate scripts to run the point tools that do. "The user's only interaction is to choose the IP and enter the specification," said Jussel. "The system then runs the tools automatically, and the user doesn't have to create scripts."
As with simulation test vectors, QuickUse can bring manufacturing test concerns to the top level of the chip. For physical design, QuickUse adds the ability to bring in hard cores automatically, and it generates tool scripts to drive timing-driven placement and routing.
Pricing is based on an initial license fee of $200,000, plus the projected level of customization.