KYOTO, Japan CMOS process technology titans Intel Corp. and IBM Microelectronics clashed at the Symposium on VLSI Technology this week over the benefits of silicon-on-insulator (SOI) technology for microprocessors, with IBM making claims of performance increases over 30 percent and a readiness to move into volume production, while Intel threw cold water over the long-term benefits and questioned its manufacturability.
During a roundtable discussion here, it became clear that there are still deep divisions over SOI, a technology that has been a topic of discussion in the industry for more than 20 years. SOI returned to the forefront last year after IBM said it had resolved most of the issues related to production and reliability, and announced it would soon begin producing SOI-based PowerPC devices. Production of those devices is expected in a matter of months.
"I don't want to say we are done, but it has taken off at IBM and as we go forward it will get easier," said Ghavam Shahidi, senior SOI program manger for IBM Microelectronics Division and IBM Research Division.
Shahidi said SOI provides a performance gain of 20 to 35 percent over bulk CMOS, a claim the company intends to prove when it rolls out its first SOI-based PowerPCs.
SOI increases the basic transistor switching speed of a circuit by burying a sheath of oxide insulator material below the source and drain of the transistor to isolate it from the silicon substrate. According to IBM, that increases the current by 10 to 15 percent, and eliminates performance-limiting area junction capacitance and the reverse MOS body effect of conventional "bulk" silicon wafers.
Another compelling reason for moving to SOI, IBM says, is that CMOS scaling is becoming more difficult as the industry approaches 1-V supply voltages, when higher off-currents become intolerable. Making a switch to SOI will provide another route to performance that can't be achieved through transistor scaling.
Another key benefit is a reduction in power consumption, Shahidi said. As microprocessors start to use tens of millions of transistors, SOI will provide the flexibility to trade off the extra performance for power savings, he said.
IBM's view on SOI is not shared by all. Mark T. Bohr, director of process architecture and integration at Intel Corp. and an Intel fellow, said Intel has concluded that any performance gains derived from SOI will diminish with every process generation, and that the downsides are too numerous.
In a slide presentation, Bohr showed figures indicating that extra performance derived from junction capacitance the most compelling reason to choose SOI, he said will start with a 13 percent improvement at 0.25 micron, fall to 10 percent at 0.18 micron and then to 8 percent at 0.13 micron. Other positive aspects were marginal and offset by negative factors, such as the floating-body effects caused by the transistor being isolated from the silicon.
He concluded by saying SOI provides less than a half-generation performance gain, has too many circuit-design uncertainties, adds another 10 percent to the process cost for an extra mask step, requires pricier wafers and may lead to yield loss.
"It's still unproven for high-performance CPU applications," he said. "We see most of the SOI benefits holding constant, but the one key benefit is going to diminish."
He did agree, however, that SOI does have an advantage in preventing soft errors, an issue that has recently become a bigger concern for Intel as it scales its process technology below 0.25 micron. SOI is two to three times better than bulk silicon in preventing soft errors, which "may in the future be an argument for SOI," Bohr said.
Others from the audience, many from Intel, threw more knives at IBM, questioning the need to eliminate junction capacitance when copper wiring would provide a significant boost in performance.
Shahidi, however, argued that the use of copper does not render junction capacitance irrelevant. "You can't drive a long wire with small drivers; you have to have larger repeaters, so junction capacitance is critical," he said.
IBM officials, however, conceded that the floating-body effect does pose a problem, but said that IBM has resolved many of the issues.
"It's like a wild horse and you have to tame it," said Bijan Davari, vice president of IBM Microelectronic's Semiconductor Research and Development Center (Hopewell Junction, N.Y.) in a later interview. "We've figured it out enough to design real circuits," he said.
Shahidi, meanwhile, conceded that SOI costs 10 percent more than other process technologies. "You have to have customers willing to pay a premium," Shahidi said.
While Intel and IBM may have real disagreements about the performance attributes of SOI, a fundamental reason for their differences may lie in the markets they serve. Because of its leadership in microprocessor shipments, Intel can hardly risk moving to a new technology that may slow down its factories. Bohr suggested that an SOI implanter is limited to a throughput of 20 wafers a day, but a typical Intel fab runs thousands of wafers a week, according to other Intel sources. Moreover, Intel would be reluctant to move to a technology that could cause a yield loss as low as two to three percent, Bohr said.
IBM's Davari said he recognizes those factors as a key difference between the two companies. "[Intel] has to ramp up a significant amount of capacity at once," he said. Even so, while he wouldn't comment on his company's SOI wafer throughput, he said, "there are ways to get around that implanter doing 20 wafers a day."
Indeed, IBM plans to start ramping up production of its first PowerPC devices using SOI.
The first 0.22-micron devices will be used for Apple Computer's Macintosh systems and IBM servers, perhaps in the next two to three months. At the same time, IBM is developing a 1-GHz version based on a 0.18-micron process that will try to steal some of the limelight from Intel's second-generation IA-64 chip, dubbed McKinley.
Earlier in the week at the VLSI Symposium, IBM presented a paper describing a 64-bit PowerPC device with 34 million transistors running at 670 MHz, incorporating six layers of copper interconnect and SOI. The chip will include 256 kbytes of instruction/data level-one cache, and 104-k x 16 of L2 director cache. The 139-mm2 device has an internal 1.8-V core operating voltage, uses a 3.3-V supply voltage and dissipates 24 W.
Though IBM has not made an official product announcement of the SOI-based PowerPC, the device will be production-ready for server products in the next two to three months, once debugging is complete, Shahidi said.
Possibly before that chip is announced, IBM will start to deliver a slower-speed PowerPC 750 to Apple that uses SOI and the same process technology, he said. Each of the SOI-based processors exhibit performance improvements over previous-generation processors that are "greater than 30 percent," Shahidi said.
Meanwhile, IBM is now developing its 0.18-micron- and 0.13-micron-generation SOI for PowerPC chips. Shahidi said IBM plans to detail a 64-bit device with a 1-GHz clock at the Hot Chips conference at Stanford University in August, and may announce its 0.18-micron SOI process technology later this year at the International Electron Device Meeting. The 1-GHz device will be used in IBM's RS/6000 server series. The chip is slated for introduction in 2001, and will go toe-to-toe with Intel's McKinley processor, he said.
McKinley is expected to appear late in 2001. Initially, Intel will use a 0.18-micron process technology, but is expected to quickly migrate to a 0.13-micron process with copper interconnects the following year.
IBM was able to cut channel-switching delay using SOI and thereby boost chip performance significantly over its current copper-based PowerPC chips that use bulk technology. Shahidi said a ring oscillator circuit, a benchmark widely used in the chip industry to measure transistor speed, has delay of less than 10 picoseconds with a channel length of 0.12 microns using a 0.22-micron CMOS process. That's comparable with transistor speeds exhibited by Intel's 0.18-micron process based on bulk CMOS, which uses shorter channel lengths because of its smaller line widths, he said.
IBM's SOI technology employs a partially depleted insulator that is about 1,000 angstroms thick, which is about double the thickness of fully depleted material used by other companies such as Motorola, he said. Shahidi said there are several advantages to using partially depleted devices compared with a fully depleted approach, including the ability to use multiple threshold voltages, better manufacturing characteristics and good scalability.
While IBM is moving forward, still others are sitting on the fence. Samsung Electronics has tested the waters by fabbing a 0.3-micron, 16-Mbit SOI DRAM with a buried capacitor, and observed lower operating current and a 27 percent power dissipation. But there are many drawbacks to using the technology, including a degradation of dynamic retention time, uncertainty over floating-body effects, problems achieving wafer uniformity, defects and price.
But Samsung continues to press forward. "[SOI] still has many advantages, and we're trying to minimize the problems," said Jeong-Seok Kim, a researcher with Samsung Electronics.
Just as analog engineers are looking at SOI as a way to isolate their designs from digital on the same chip, it may also be useful for on-chip DRAM. "In embedded DRAM, if you use a thick SOI layer you may have good signal and thermal isolation from logic," said Jeong-Mo Hwang from the R&D division at LG Semicon Co. Ltd.