SAN JOSE, Calif. Allayer Technologies Inc. is living up to its name by being one of the first enterprise switching-chip players to move to true Layer 3 Internet Protocol (IP) routing functions in a chip that includes a packet parser, search engine, and DMA-based management engine. The AL3000 IP Routing Engine is being introduced simultaneously with the AL126, a new eight-port Ethernet/Fast Ethernet switch chip that operates on the RoX-II bus a 100-MHz upgrade to Allayer's "Ring of Switches" (RoX) architecture.
The debut of an IP routing engine for enterprise applications is the first step toward the eventual edge-routing WAN chips that Allayer will provide, said company president Cheng-Chung Shih. Even now, the AL3000 can be used in standalone fashion as a network coprocessor, though its primary application is in implementing low-cost Layer 3 switches for enterprise LANs. Routing prioritization functions have been hard-wired in the state-machine-based design to insure higher performance than programmable route processors.
The AL100A switches that implement the first-generation RoX will not be made obsolete by the rollout, as Allayer expects a market for the AL100A and RoX-I for at least two more years. In fact, recent tests by Silicon Valley Networking Lab Inc. showed that the first-generation switches showed no head-of-line blocking in 24-port implementations, and no frame losses in full mesh networks. Nevertheless, the earlier switches will be devoted to entry-level Layer 2 switch designs.
Shih said that it was important to plan for simultaneous sampling of the AL126 eight-port switch for RoX-II, and the AL3000 for IP routing. The former device allows workgroup switches to add more complex Layer 2 packet control, such as four levels of 802.1p packet prioritization, 802.1Q VLAN tagging and multicast support. It also supports the emerging 802.3ad standard for Ethernet trunking, and allows both the creation of trunk channels and the automated implementation of link failover without any host CPU intervention. In normal mode, the AL126 can support 12,000 MAC addresses, which expands to 16,000 MAC addresses when 802.1p and Q are disabled.
Allayer decided that four levels of priority were sufficient for the AL126, but allows other means of programming packet ordering by queue or by port. There is an optional weighted round robin queue algorithm which can be implemented, as well as an optional early packet discard per queue for congestion control.
The companion AL3000 legitimately can be called a Layer 3 and 4 engine, since it allows packet header searches based on source and destination addresses at the MAC or IP layers, as well as Layer 4 TCP and UDP socket assignments. The on-chip search engines relies on external SGRAM, expandable from 4 to 8 Mbytes depending on the desired table size. A separate 2-Mbyte bank of SGRAM is used for the packet memory for queuing algorithms.
Allayer had originally planned for an independent AL300 management device that would contain all counters for Simple Network Management Protocol and Remote Monitoring management information bases. But the company decided at the last rev of AL3000 silicon to embed all AL300 management functions inside the larger IP router device. The end result is a 456-pin device in a BGA package, representing Allayer's most complex product to date.
The AL126 is also housed in a 456-pin BGA. Both devices are sampling now with production set for September. The AL3000 costs $85 and the AL126 costs $40 in quantities of 1,000.