TOKYO Sharp Corp., a major player in chip-scale packages (CSPs), has developed a CSP able to stack three chips in a single package to create a kind of system-on-chip package.
Sharp, which has offered CSPs that stack two chips since April 1998, believes the expanded package is "the first step to integrate a system in one package," said Morihiro Kada, general manager of the Packaging Engineering Department at Sharp's Integrated Circuits Group. "It's not just that the number of chips being stacked has increase from two to three. We believe that this will be a tool for system integration," Kada said.
Numerous semiconductor manufacturers are now working to integrate as many circuits as possible into large-scale system-on-chip (SoC) designs. "That is a horizontal solution," Kada said. "We will provide a vertical solution."
Compared to a single-chip SoC design, a stacked-chip solution is practical, available and inexpensive, Kada said. The package can house various combinations of chips, depending on the application. It can enable the doubling or tripling of memory capacity in one device, or can house memory along with a CPU. Such solutions can be achieved without waiting for finer process technologies that would be needed to integrate the same circuitry on a single silicon die, Kada said.
The package's first main target will be cellular phones, which could use a combination of flash memory, SRAM and a CPU, or two flash chips and one SRAM.
Flash memories used in cell phones are currently in tight supply, especially the larger-capacity 32-Mbit parts needed by next-generation cellular phones to implement sophisticated functions. Sharp's stacked package can create a higher-capacity device by combining older-generation memories, such as 16-Mbit flash chips, into the package.
The package's biggest advantage is compactness, Kada said. A 32-Mbit flash, 16-Mbit flash and 4-Mbit SRAM housed inside the new package has a footprint of 90 square millimeters. By comparison, bare chips in the same memory combination occupies 159 square millimeters.
Stacked logic and memory chips are lighter and smaller than bare chip combinations, according to Kada. The three-chip CSP weighs 0.83 grams, while bare chips weigh 1.27 grams, he said.
Since 1 gram can make a difference in the fiercely competitive cell phone manufacturing arena, Sharp's packaging solution could be a significant help to manufacturers trying to deliver lightweight portable phones in 50- to 60-gram range, Kada said.
Sharp intends to offer the three-chip stacked CSP at a price similar to three single CSPs. Sampling has already begun and volume production is scheduled to begin in August.
Sharp has been working to establish its two-chip stacked CSP package as a de facto solution for holding flash and SRAM for use in mobile systems. Intel Corp. and Hitachi Ltd. agreed earlier this month to support the specifications used by Sharp and Mitsubishi Electric, which had earlier decided to use Sharp's specification.
Sharp's three-chip package is highly customizable, Kada said. Specifications such as pin layout, number of pins and pin pitch may all be decided by customers. Sharp is preparing with 200-pin package with an 0.8-mm pitch as its first offering.
Sharp, a major supplier of flash devices in Japan, wants to use its flash memory in the three-chip stacked CSP. Sharp will also consider taking in designs from outside companies, though Sharp has no desire to take orders as if it were a packaging company, Kada said.
The stacked-chip package is flexible in terms of shape and size of the three chips it hold, as long as the stacked chips do not interfere with wire bonding. The first, bottom chip is bonded normally (from chip to substrate), and the second and third chips use a reverse bonding (from substrate to chips) to avoid crossing the wiring of each chip.
Wire bonding of memory chip combinations is rather simple because data and address output are usually unified. But wiring becomes more complex with a logic and memory chip combination, because a logic chip has bonding pads on all sides while a memory chip uses two sides.
Within Sharp, design engineers have already started designing chips with the assumption that they will be stacked. "Packaging is leading chip design," Kada said.
Sharp will make a presentation on its three-chip stacked CSP at Chip Scale International, which will be held Sept. 13-16 at the San Jose Convention Center, San Jose, Calif.