TSUKUBA, Japan A research project at the Electrotechnical Laboratory (ETL) has devised an adaptive clock circuit that could address the expected yield problems for gigahertz processors by canceling out fabrication variations.
"Our simulations show that the yields of 800-MHz chips can be increased from 2.9 percent to 51.1 percent after our clock-timing circuits are evolved by genetic algorithms," said researcher Eiichi Takahashi of ETL, based here.
Takahashi performed the work in cooperation with fellow ETL researchers Masahiro Murakawa, Kenji Toda and Tetsuya Higuchi. The four presented a paper on their findings at the recent Genetic and Computational Conference in Orlando, Fla.
Though Intel Corp., Motorola Inc. and Digital Equipment Corp. closely guard the yield figures for their respective Pentiums, PowerPCs and Alpha microprocessors, the ETL researchers claimed that those manufacturers have suffered yields as low as 10 percent on microprocessors over 500 MHz. If the problem isn't addressed, they warned, yields could dip below 3 percent by the time chip speeds hit the GHz range.
"The timing delays from the random variations in parasitic capacitance and resistance along data lines are causing out-of-specification flaws, [causing] a large proportion of new chips with clock speeds over 500 MHz to fail during testing," said Takahashi. The ETL researchers thus designed components that can be integrated onto high-speed chips to correct for random variations in parasitic capacitance and resistance.
The circuitry includes "chromosome" registers, which can be "evolved" in real-time on new chips to adapt their timing delay lines and thereby perfectly compensate for the random variations in clock skew (parasitic capacitance and resistance).
Ordinarily, when clock skew is too far out-of-spec, the errant chips are simply discarded. But the ETL technique allows such chips to be evolved to compensate for the skew. Even chips that are within spec can be evolved, either to increase their safety margins, and thus "militarize" their specifications for harsh operating environments, or to increase clock speeds beyond original design specs.
The adaptive clock circuitry that ETL designed for its test chips uses a digital delay mechanism under the control of a 5-bit chromosome. For example, the chromosome represented by the string "00001" inserts a delay of one, whereas a 10001 chromosome inserts a 17-unit delay. The delay unit size depends on the specific chip. Chromosomes are initially set at half-speed (01111) so that both positive and negative delays can be evolved to compensate, respectively, for lines that are too slow or too fast.
The most novel aspect of the ETL approach is its "fitness" function, which controls the evolution of the chromosome values by measuring chip performance, rather than the actual delays of individual data lines. The individual delays of internal data lines cannot conveniently be measured other than by boundary scan or other indirect techniques. The ETL researchers sidestepped the problem by measuring the performance of the chip in meeting its design specifications, instead of measuring the delays along internal delay lines.
The chromosome registers were connected together as a long 1,000-bit shift register, so that new chromosome values could be shifted into the chip-wide shift register in about 1 second at 1 MHz. The procedure, as with all genetic algorithms, first placed random values in all the on-chip delay line chromosome registers.
In its initial tests, ETL began with a population of 50 random 1,000-bit chromosome values. It shifted each of the initial settings into the chip in turn and then measured the performance of the chip in meeting its design specifications. The settings that yielded the best specs were retained and the others discarded.
The values of the good sets were then slightly mutated and combined with one another using artificial sex called crossover, since the beginning of one chromosome set is crossed over to end with the last part of another chromosome set. After a new population of 50 "improved" chromosome sets was created, the whole process was repeated.
The researchers reported that it took only 20 such "generations" for evolution to come up with an optimal setting for the chromosomes on any particular chip. The results of ETL's simulations showed a 1,762 percent increase in yields, plus a militarization of the best chips, making them less sensitive to internal timing margins and more robust when faced with changes in power voltage and temperature.
The researchers are extending their simulation results to an 800-MHz test chip that they hope to complete before 2000.