ATLANTIC CITY, N.J. The ATE industry is gearing up for a period of prosperity, but there is serious trouble ahead unless the industry drops long-held testing shibboleths and prepares for a future in which the key drivers are the Internet and the consumerization of the electronics industry. That was the clear message emerging from the tumult of the International Test Conference (ITC), now underway here.
"The ATE industry soon could be as obsolete as the minicomputer industry, unless it responds to what we need," said keynoter Pat Gelsinger, vice president of Intel Corp.
"The chips are leaving the testers behind, except for a role of correlation and validation," said Gelsinger, who predicted an end to the fully-featured, do-it-all ATE system.
"The test gap" is caused by more than the rocketing speed of processors, said Ned Barnholt, chief executive officer of Hewlett-Packard Co. New defects arise from shrinking chip features sizes, sizzling power draw and dissipation, steep current transitions and the cost of testing compared to the shrinking sales price of the device under test, Barnholt said.
"Although there's been a hundred-fold increase in DUT [device under test] speed, tester speeds have increased only tenfold," Gelsinger said. He spoke of 200-watt processors and 60 Amps/nanosecond di/dit going through a device operating at close to 1 volt and called for "a new paradigm for power delivery during test and for test overall."
In addition, Gelsinger warned of new defect populations in deep-submicron chips, "causing failures because of sensitivity to Vcc, temperature and frequency."
As for test costs, Gelsinger pointed to the extreme pricing pressure on components because of the Internet explosion and the move to e-business. "The cost of manufacturing test is not scaling," he complained, "and the quality of test is not sufficient. Companies cannot afford to have their Web sites go down."
Joe Irick, vice president of field marketing for Schlumberger ATE, took exception to Gelsinger's analysis of test costs as normalized on a per-transistor basis. "We have slashed the raw cost of test by half since the early 1990s and bolstered performance by a factor of eight. Intel's speed road map is well within our capacity, so there is no short-term issue. Three to five years out, when speeds go into the gigahertz regions, we'll need new test methods. What, is still unclear."
But Irick agreed with Gelsinger's call for more testing at the burn-in stage. "That is the most significant opportunity to reduce test costs and cycle time, but it's not fully proven as a single strategy," Irick said.
Other ATE suppliers are either evaluating or offering that very approach. Unisys Corp. (Chandler, Ariz.) showed a burn-in system at ITC that offers a substantial capacity for JTAG testing of multiple chips during temperature soaking.
Another way to cut costs is to test as many chips as possible in parallel on one machine. The semiconductor industry has been pushing for that and, at least for memories, has succeeded in pushing the ATE vendors to supply multi-site machines. DRAMs, for example, can be tested at 64 parallel sites, and Advantest Corp. said it would be going to 128 sites soon, on two stations. "We are going faster than Moore's Law," said Nick Konidaris, president of Advantest America Inc.
Tom Newsom, vice president of marketing for Agilent Technologies, said that one figure of merit for test which factors in pin counts, frequencies, accuracy, throughput and up-time showed a gain of over 50 in the last eight years. And he noted that the cost of test had dropped on a per pin basis over that same period.
"But the way to solve the chip test cost and technical problems is to work smarter by taking advantage of Moore's Law," Newsom said: "Use SoCs to test SoCs."
Not surprisingly, Agilent has done just that in a system-on-chip (SoC) tester in which most of the critical timing and other important blocks occupy one piece of silicon. That way, the tester can sit close to the DUT, run faster, eliminate cabling delays and parasitics, reduce parts count, and offer an unlimited pin count. In addition, the power supplies can be relocated to the test head.
Though few at ITC believe the ATE industry will self destruct, Gelsinger had company that believed something has to change.
"As emerging market trends continue to mandate faster, more complex devices with shorter life cycles, there is growing pressure on semiconductor manufacturers to find new test solutions that allow them to move quickly to high-volume production," said Risto Puhakka, vice president of VLSI Research Inc.
Even the Semiconductor Industry Association itself has recognized the crucial role of test. "Time-to-yield, time-to-money, time-to-quality, time-to-market are all gated by test," an SIA spokesman said.
To George Chamillard, chief executive officer of Teradyne Inc. (Boston), the leading U.S. ATE vendor, developing new semiconductors is a risk, and so is developing new ATE systems targeted at those new chips. "We need to find a new way to share those risks," Chamillard said.
Irick agreed. "We cannot be just suppliers anymore," he reflected. "The semi vendors must enter into a true close-knit partnership with one or two of their test suppliers; otherwise, it will be difficult for both industries to go on."
But some semiconductor manufacturers have found an easier solution to the problem of volume testing: cut back, or don't test at all. "One major vendor is pushing test on its customer base," said Dan Hutcheson, president of VLSI Research.
One school of thought suggests that testing devices on motherboards may be the way to go. Kingston Technology has used that approach in the search for better quality and lower test costs.
"Testing devices in motherboards sounds good," said Irick, "but I don't know of any manufacturing strategy that has made it work."
Minimal testing may 'work' for chips going into PCs which likely also receive minimal testing in the rush to ship, but what about chips going into mission-critical applications, such as automobile braking and steering systems? PC manufacturers take back a bad unit, no questions asked, and ship a new one. But what will car makers do when inadequately tested chips begin to cause accidents, perhaps fatal accidents?
The ATE industry is struggling to catch up, and is largely succeeding for the short term. Support is improving for faster speeds, greater accuracies and higher pin counts. Economic pressures are causing the price of capital equipment to come down. Test systems are shrinking in size. All told, that may not be enough for the future. For test, the big chips have become moving targets, and even the most accomplished test sharpshooters are not certain how to hit the bullseye.
Gelsinger had some additional solutions: greater use of structural test, such as BIST and more advanced ATPG to uncover submicron defects (although he admitted that Intel had to use functional testing to detect faults that ATPG failed to find); innovative test manufacturing integration; improved fault simulations; new materials and ways to achieve very low inductance and resistance at the DUT/ATE interface.
Some of that is happening, such as Credence's use of BIST techniques on a DUT's load board. Certainly, the big ATE guns that Advantest, Credence, Hewlett-Packard, Teradyne and Schlumberger brought to the International Test Conference are armed with new capabilities aimed at systems on silicon, the new fast memories, and mixed-signal chips. But these test weapons could be duds for chips lurking around the year-2000 corner.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.