HSINCHU, Taiwan With line widths shrinking and total transistor count growing, communication between chips within a system is becoming the weak link in the chain. A Taiwanese startup has opened an advanced facility dedicated to emerging die-to-die packaging technologies that strengthen that bond.
APack Technologies Inc. is wrapping up sampling and customers' audit production for its chip-on-chip, flip-chip assembly process. Initial products include DRAM modules, flash/SRAM modules for the telecom market, and chips that use copper interconnects from Taiwan Semiconductor Manufacturing Co. .
"One of the first products we will be assembling is a combination of flash and SRAM chips," said Sebastian Liau, vice president of R&D for APack. "We are doing the chip-on-chip packaging for a Japanese company that will use the product for wireless handsets."
Liau added that "TSMC is using our wafer-bumping technology for their copper interface chips. The top two layers of the wafers TSMC delivers to us have copper interconnects. We do a copper bump on top of these ICs."
TSMC is also working on a bump-packaging approach in-house. "APack is one candidate for such advanced packaging technology," said J.H. Tzeng of TSMC. "We will also do bump packaging on our own with a small line in our Fab 1 facility."
APack will begin to package DRAM modules using its bump technology in the first quarter, delivering the chip-on-chip wafers as "tiles." "A 60 percent improvement in DRAM speed is easily obtainable using our packaging technology," said Albert Lin, senior vice president at APack. "The speed increase depends on the IC's original design. If the design is optimized to take advantage of our bump technology, then a standard 133-MHz SDRAM can transfer data at 650 MHz."
Board limits speed
Traditionally, an IC's pins were the limiting speed factor in a system design. Using flip-chip and bump solder technology, the limiting factor becomes the pc board. "The line width and length of a PCB will be the limiting hurdle now," said Lin. "Our technology helps to solve that, but PCB designers will need to take the new flip-chip technology into consideration when designing boards."
APack is also looking ahead to working with IC designers. "We can do some rerouting with our masks to optimize the performance of an IC," said Lin. "The next step, though, is to optimize the IC design in order to take advantage of the chip-on-chip bonding."
APack will use its chip-on-lead-frame technology for DRAM and flash card customers; chip-on-chip technology initially will be used only for the telecom flash/SRAM chips. Commercial production will begin this quarter. Full production of Phase 1 will be up by the second quarter.
At the moment, APack is packaging about 8,000 8-inch wafers per month. The company has the space, however,to ramp up to 50,000 wafers per month. Lin said APack can install additional equipment into the 29,000- square-foot clean room in about four months.
In the future, APack wants to provide system-on-package technology. "We can provide the technology," said Lin. "It's a matter of the market wanting it. Lucent and IBM are pushing the technology. The Japanese also are very interested."