ISSCC: Toshiba reduces RDRAM die size

YOKOHAMA, Japan — Toshiba Corp. will disclose a plan on Wednesday (Feb. 9) to reduce the cost of manufacturing high-speed Rambus DRAM chips by modifying the core design to be 8 percent smaller than normal.

The 0.175-micron, 288-Mbit RDRAM, which will be described at the International Solid State Circuits Conference (ISSCC) in San Francisco, will begin sampling this spring. Toshiba also plans to use the design for later versions of its 144-Mbit Rambus memory, which is just coming on stream.

Reducing RDRAM core size by 8 percent will not make the die size — a key factor in determining manufacturing cost — equal to that of lower-cost SDRAMs, which can be more than 20 percent smaller than 800-MHz RDRAMs. But to Toshiba, it is a step in the right direction to make RDRAMs a mainstream product.

Most of the die real estate savings comes from reducing the area required for peripheral circuitry. This was done by shifting the cell array 90 degrees to create the four 72-Mbit quadrants that make up the DRAM array. Each quadrant is made up of independent banks that run vertically to the chip's length rather than horizontally as they do with conventional designs. That allowed Toshiba to push much of the control and peripheral circuitry, such as the shift column decoders, shift registers and second-sense amplifiers, to the middle of the chip.

One of the immediate advantages of this architecture is that it will allow Toshiba to cut a 288-Mbit device into two 144-Mbit RDRAMs. "In a conventional structure, we would have had some problems creating cut-down products with half-memory cores. We could do something similar, but we would have to redesign the shift registers, and that is an especially laborious procedure," said Hideo Mukai, a researcher with Toshiba's Advanced Memory Design Development Department here.

No penalty

There's also no die-area penalty for implementing 2-kbyte page sizes, which Mukai said will consume more power but will be desirable for high-end workstations. "Two kbytes is a sort of requirement for 256-Mbit DRAMs," Mukai said. "We could offer both using a conventional architecture too, but we would need additional circuitry for current operations, so it would increase the die size."

Toshiba was able to avoid using new circuitry for that purpose by making the sense amplifiers do double duty. Within each 72-Mbit quadrant are four groups of 16-bank strips. When two adjacent strips are activated, the 1-kbyte memory is activated. When two pairs of the strips are activated, 2-kbyte pages are applied.

Moreover, Toshiba designed the core so that the memory banks would share many of the same shift registers and second-sense amplifiers. Placement was also important. Normally, rows of sense amplifiers are placed side by side and divided by row decoders, creating a break between the rows. In this scheme, they are placed horizontally so that die area can be used more efficiently.

Toshiba has perhaps one of the largest stakes in RDRAM production because of its relationship with Sony Computer Entertainment. Toshiba is co-developing the main processor for Sony's Playstation 2 and is supplying the Rambus DRAMs that will be used in the system. The company also recently started shipping its first 144-Mbit RDRAMs to PC customers last month.

Toshiba claims its yields have improved to the point where RDRAM manufacturing is feasible, but it still has a strong incentive to bring the cost down closer to commodity DRAMs.

"In order to popularize RDRAMs, we definitely need to reduce production cost by area reduction," Mukai said. "This is 10 percent larger than SDRAMs. But in the case of a 256-Mbit [device] in a conventional design, it was 20 percent or more."