SAN JOSE, Calif. One of the more exciting papers presented at this week's Embedded Processor Forum was not about a processor, but about a novel digital I/O scheme.
Jim Slager, chief evangelist with Jazio Inc. (San Jose, Calif.), said the approach could shave a third of the power off chip I/O consumption. The technology could enable signal pin frequencies from 1 GHz to 4 GHz while keeping signal slew rates at contemporary or lower levels, he said. Jazio is exploring licensing options with a number of major companies and is considering requirements for standardization for future DRAM architectures with Jedec.
Slager, a respected microprocessor designer with spells at Sun Microsystems and Hitachi, said the Jazio interface architecture could also have important implications for on-chip buses, though his presentation addressed only the off-chip application of the interface.
Traditional bus signaling is based on a low-voltage "zero" and a high-voltage "one" in near-to-square wave switching, but as clock frequencies have increased more power is wasted in maintaining the classic signal form and its resulting effects, including ground bounce, crosstalk, ringing and electromagnetic interference.
Reduced voltage swings, differential signaling on two wires, and psuedo-differential signaling on one wire, have all been used to reduce sensing levels, but after trying all those approaches, Slager said, "all of the information is transmitted during about a third of the bit time; the rest of the time is just wasted."
Jazio technology is a patented variation on low-voltage differential signaling. The scheme is transition-sensitive rather than level-sensitive, and requires only one pin per signal accompanied by two complementary free-running clock-like signals. These are: the voltage timing reference (VTR) and its complement, VTR-bar. These signals ramp up and down in sequential clock periods.
Jazio's contribution is to invent a scheme that compares the data with VTR and VTR-bar and uses the outputs to check whether a transition has occurred. The steering logic that copes with differential comparison is 55 small-signal transistors and occupies an area considerably smaller than a bond pad in contemporary process technologies.
Slager said that the technique minimizes slew rates, which can cause signal-integrity problems and, because it is so deeply and completely embedded in the physical layer, is applicable to any higher order communications protocol such as RapidI/O, or double-data-rate DRAM or Rambus DRAM.
Jazio recommends a sensing differential of about 500 mV compared with 800 mV or more for psuedo-differential signaling and the inclusion of a VTR and VTR-bar for every 18 data lines.
"If you want to go wider that's fine, but we suggest replicating VTR and VTR-bar," Slager said.
In his talk Slager emphasized that most of the information to enable engineers to design with the Jazio interface will be put in the public domain, but said that Jazio demands a license agreement before any chips are shipped.
Asked how Jazio would police its patented technology, Slager said: "I don't think anyone would want to rip us off. Certainly, to use the technology and risk being prosecuted later would be very dangerous."
If used with DRAM, Jazio has suggested a lifetime license fee of $200,000 and a 0.3 percent royalty for each DRAM sold, though the Jazio interface is applicable to any digital logic chip.
Slager said that Micro Magic Inc., a design services company, is building a test chip to prove the Jazio technology. The company is using a 0.18-micron process technology and expects to get Jazio pins toggling at 2 GHz. Silicon is expected next month and samples should be available to potential licensees in the fourth quarter.
Slager said a move to 0.13-micron technology should double the performance of the Jazio interface.
Vojin Oklobdzija, a professor in the department of electrical and computer engineering at the University of California, Davis, with experience in I/O circuit design said, "Standard ECL on bipolar uses an 800-mV signal swing on-chip. Using 500 mV off-chip is very advanced and the power savings are obvious. It's very good."
Jazio can be used for on-chip buses, Slager added. "It can do that," he said. "If you think of highly-integrated SoC [system-on-chip] designs with on-chip memory and very wide buses, there are great opportunities. But first I've got to persuade people it's a good idea going off-chip."