SAN JOSE, Calif. The two programmable-logic titans, Altera and Xilinx, are lining up heavyweight CPU and intellectual-property partners in an attempt to propel high-density PLDs into communications and embedded designs, areas previously ruled by ASIC vendors.
This past week, Xilinx Inc. and IBM Corp. announced a deal to meld Xilinx's Virtex-II FPGAs with IBM's PowerPC cores. Xilinx (San Jose) will license the rights to the cores and the CoreConnect bus, in a relationship that may expand to other "hard" intellectual-property (IP) cores.
Also, Xilinx will enlist IBM as a foundry, initially manufacturing Virtex-II FPGAs with the PowerPC cores at 130-nanometer (0.13-micron) design rules. However, the open-ended agreement is expected to include manufacturing of a wider number of Xilinx parts later on.
Meanwhile, Altera Corp. is in negotiations for its own PowerPC license, from Motorola Inc. "We would expect to close that discussion in three months," said Cliff Tong, vice president of corporate marketing at Altera. That company, also based in San Jose, recently unwrapped its Excalibur program, which aims to blend ARM, MIPS and Altera's own Nios processor cores into Altera's Apex programmable FPGAs.
Xilinx's PowerPC deal complements a recent decision to optimize a 32-bit processor from ARC Cores Ltd. on Xilinx FPGAs. While the PowerPC deal aims at hard cores that deliver high performance, the ARC cores would be "soft," or synthesizable, cores.
Indeed, blending hard and soft standard cells on FPGAs represent a new direction for the FPGA vendors as they stake claims to the emerging system-on-chip business a market that Altera has dubbed "system-on-a-programmable chip."
If successful, the efforts by the two PLD giants would make it possible for design engineers to develop processor-based designs that offer the time-to-market advantages and low nonrecurring-engineering costs of FPGAs, without sacrificing too much performance clout.
"We are at a turning point," said Rodney Smith, Altera's chief executive officer. "In the past we supplied reprogrammable logic in larger and larger chunks. What we are doing now is supplying a large processor and memory in a reprogrammable chip."
Wim Roelandts, chief executive at Xilinx, said his company's deal with IBM has a focused goal: using hard cores to wring higher performance out of FPGAs, especially for networking applications. "[Altera is] talking about 150 Mips, but we're talking two or three times that performance," Roelandts said.
Xilinx and IBM are not offering a retargetable, VHDL implementation. Rather, they will offer optimized PowerPC cores, instantiated in the middle of a die built with IBM's best process technology. While the partners are not discussing which PowerPC core will be offered first, Roelandts said it will include a standard array of interrupts, memory controllers and other functions essential to building a system-on-chip. Surrounding the PowerPC will be an FPGA fabric.
John Kelly, general manager of IBM's Microelectronics Division, said that initially IBM will manufacture Xilinx FPGAs equipped with the PowerPC cores, but that the foundry relationship could broaden to include standard Virtex-II products. Also, Kelly emphasized the CoreConnect portion of the deal.
"CoreConnect provides a bus structure that could be a glue here to other blended chips, where Xilinx could offer other hard macros," he said. Since CoreConnect is an open bus that can be licensed from IBM at minimal cost, that opens the door to commercial IP offerings as well.
Greasing the skids
Thus far, the nascent effort to offer either hard or soft IP cores on PLDs has been slow to take off, with one notable exception: PCI cores. But if processor cores and well-understood bus structures travel into the FPGA world, they would grease the skids for wider use of IP on FPGAs. Process advances will buttress the trend, as 100-nanometer (0.1-micron) CMOS expected by 2003 improves FPGA density and speed.
"We used to say there is a $20 billion logic market, of which 10 percent is for programmable parts," said Altera CEO Smith. "Now we are targeting a $50 billion market for embedded systems, out of which programmable parts currently have a zero percent stake. We are at the infancy of that opportunity."
Altera will not have its full Excalibur offering ready until the end of the year, and Smith said the company does not yet have any early customers. Nevertheless, he predicted the trend ultimately would represent a huge threat to mainstream semiconductor makers.
"The broad-based supplier of multiple products will disappear," Smith said. "Very low-volume custom parts are simply not cost-effective."
His counterpart at Xilinx agreed. "By putting a processor on the same die we can penetrate the embedded-control marketplace," Roelandts said. "The logic market, including ASICs, FPGAs and standard cells, is a $23 billion market. Embedded control is a $24 billion market, so we are in effect doubling our market opportunity."
Success rides on the well-worn horns of performance and cost. Xilinx's licensing of the PowerPC "does put them way up there" in terms of performance, said Murray Disman, principal analyst at Information Associates (Menlo Park, Calif.). "Some of the PowerPCs are 400 or 500 Mips."
Xilinx is leapfrogging low-power designs, where a processor core such as ARM's might be a better fit than a PowerPC. "Xilinx will come out first with the really high-end stuff, and then they'll probably fill out the lower end," Disman said.
While ARM cores ship in high volumes in cellular phones, the PowerPC is a more important platform in cellular basestations, routers and switches, and other systems that use FPGAs, Roelandts at Xilinx argued.
Indeed, Xilinx picked the PowerPC expressly because IBM has been looking for new ways to expand its use in embedded communications applications. "The PowerPC seems to be used more in the communications space than any of the other processors," Roelandts said. "That's why we chose to do PowerPC first."
The foundry portion of the deal augments Xilinx's foundry agreements with United Microelectronics Corp. (UMC) and Seiko Epson Corp.
IBM, UMC and Infineon Technologies agreed late last year to co-develop compatible process technologies at the 130-nm and 100-nm technology nodes that would allow customers to move designs among the three companies, providing foundry portability. At 130-nm design rules, the process was developed largely by IBM, with the help of Infineon engineers working at IBM's East Fishkill, N.Y., facility.
UMC essentially licensed that process and will market it as its World Process next year. Xilinx's close relationship with UMC would give it access to IBM's manufacturing technology anyway, but the new deal gives it first crack at IBM's process advances, some of which such as silicon-on-insulator IBM has kept separate from the Infineon-UMC co-development work.
"IBM is the world leader in CMOS technology," Roelandts said, "and this gives us access to that technology earlier than if we only had UMC." Roelandts said that "over time," UMC also will gain rights to make the Virtex-II parts with the PowerPC cores.
Another concern in gaining access to IBM's manufacturing capacity for the Virtex-II family is "geographical balance," he said. Though Xilinx has a longstanding relationship with Seiko Epson (Nagano, Japan), it relies heavily on UMC in Taiwan, raising some customers' fears about earthquakes.
"My concern is not so much an earthquake," said Roelandts. "Over the long term we have to [have manufacturing close to] all the major markets."
Roelandts said Xilinx and IBM make a good fit as business partners. "We are, for the high-volume customers, mainly used for prototyping. We know these customers will go to an ASIC," he said. "Therefore, a collaboration with an ASIC company is a benefit for both. We get more prototyping business, and they, for customers with lower volumes, can say, 'Why don't you stick with an FPGA?' "
Analyst Disman agreed that the deal was a good way to share customers, using Xilinx parts to prototype IBM ASIC designs or even replace them, in the case of customers unwilling to pay ASIC NRE expenses. That possibility isn't lost on other cores vendors.
"One of the things MIPS [Technologies] really wants from Altera is a prototyping vehicle for people who are using the MIPS core in an ASIC," Disman said.
Peter Feist, vice president of marketing with PLD vendor Quicklogic Corp. (Sunnyvale, Calif.), predicted that 90 percent of the customers working with both Xilinx and IBM would wind up keeping their designs in programmable logic, with only 10 percent going to an IBM ASIC.
"Maybe they hope that by licensing PowerPC to Xilinx, they can proliferate that technology," Feist said. "Everybody thinks their design is going into millions of units, but if you look at who's converting it's nobody."
Turnabout is fair play
As the FPGA vendors work to bring processors and other IP cores onto FPGAs, the ASIC vendors are moving to add small FPGA blocks on their standard-cell ASICs. Lucent Technologies' Microelectronics Division and LSI Logic Corp. are expected to offer FPGA capabilities for designers that need to alter glue logic on a large design.
And even though the deal with Xilinx does not give IBM a Xilinx technology license, IBM's Kelly said the company is studying ways to offer small blocks of FPGA on its system-on-chip devices and ASICs. "That is something that intrigues us a great deal, and it does offer us another degree of freedom if we can do it," Kelly said.
"IBM is clearly set to move in that direction," said analyst Disman. "This deal of IBM's with Xilinx would really help that along."
Roelandts said that besides its large customers in communications, Xilinx has "thousands of customers that need only a few thousand chips per year. They are likely to stay with programmable logic for their designs, for uses including networking, robotics, medical and industrial applications. For those kinds of volumes, they cannot afford the mask costs and NRE charges [required to make an ASIC]. Their volumes do not justify an ASIC."
Overall, Disman doesn't see these alliances changing the dynamic of the FPGA-ASIC relationship. "In the early days and even right now, they're most effective competing with the gate arrays," Disman said of the programmable devices. "They're going to nibble into the cell-based stuff, where people can't afford the NREs."
But chip analyst Andrew Allison said the Xilinx-IBM deal will "bring about a new design era combining programmable logic's time-to-market advantages with the cost benefits of standard-cell technology. This is a potent combination."
Additional reporting by David Lammers