LONDON At the Microprocessor Forum this week, ARC Cores Ltd. is set to announce its Tangent-A4 processor architecture.
The architecture consists of a configurable processor and a set of peripherals that will be offered as licensable intellectual property in the first quarter of next year, and represents ARC Cores' attempt to extend configurability from the compiler and processor level up to a richer system or platform level.
ARC (Elstree, England), a mid-'90s spin-off from PC games software maker Argonaut Games plc (London), pioneered the concept of a 32-bit RISC processor with selectable attributes already accounted for within a configurable C language compiler. ARC claims to already have 50 licensees for versions of the ARC processor, and several U.S. companies have followed ARC into the configurable processor field.
ARC executives claimed that with the Tangent-A4 they would take the point of configuration to a higher-level of abstraction that includes system-on-chip peripherals targeted at key applications and covers development issues including cycle-accurate simulation, real-time operating systems and driver software.
"With software and hardware building blocks from ARC's subsidiary companies and third parties, powered by the high-performance Tangent-A4 configurable processor, we're taking configurability to the system level for applications requiring DSP and multimedia support," said James Turley, vice president of marketing at ARC Cores.
The Tangent-A4, due to be presented at the Microprocessor Forum by James Hakewill, ARC's chief architect, is based on the ARC3.0 architecture he presented at the Embedded Processor Forum in May 1999. Indeed, Hakewill said that only one instruction has been added to the ARC3.0 instruction set to develop the Tangent-A4; a software-interrupt instruction. Hakewill said that most of the differences are in the periphery and in providing access and coherency across a broader development tool chain.
For example, Tangent-A4 provides compatibility to the ARC3.0 but also has a configurable data cache and enhanced DSP extensions.
The acquisition by ARC of MetaWare, VAutomation and Precise Software Technologies since the development of ARC3.0 has allowed Hakewill's team to aim at producing a coherent set of development tools that can exchange data. The development tools include the Architect processor configuration tool, the Metaware configurable C-language compiler together with a cycle-accurate simulator, a debugger and a data visualization tool.
Processor plus peripherals
"The core is only part of it. There's the processor plus peripherals, protocol stacks, codecs, Ethernet MAC, UART at up to 115 kilobits per second and drivers together with state displays that can be exported to a debugger," said Hakewill.
The pre-verified hardware and software building blocks for systems development include Ethernet, USB, MP3, DSP functions and a range of real-time operating systems including VxWorks from Wind River Inc. and MQX.
"The golden point here is about being able to provide information about program performance at the application level, the RTOS level, the C-source level, the assembly code level, and the individual signals, bits and bytes. This is important when one considers that the key objective for many new designs is accelerating time to market," said Hakewill.
However, what is not yet clear is how easily third-party peripherals could be incorporated into the Tangent-A4 Architect tool and be completely supported by development tools, or whether ARC would always expect to be able to supply a best-in-class peripheral in every area of licensee interest.
"We can continue to incorporate peripherals and enable third-parties to plug into the platform," said Hakewill.
As part of the development of the Tangent-A4 core, a configurable data cache has been brought into the configurable "Architect" system. For ARC3.0, Architect supported I-cache and x-y cache memory configurations for driving DSP version of the architecture.
"The data cache is two-cycle pipelined and can be one-, two- or four-way associative," said Hakewill, adding that this allows data to be banked to save power.
Cleaning the pipeline
Although the Tangent-A4 ISA is maintaining backward compatibility to the ARC3.0 ISA, Hakewill and his team are taking the opportunity to reorganize and clean up the four-stage CPU pipeline. "We found we could get a 20 percent improvement in some circumstances through improved interface to cache with a die area penalty of less than 1 percent."
However the company is not introducing high-end features such as out-of-order instruction execution, conditional execution or speculative execution of branches. "The philosophy is still to keep the core simple, the base core gate count is still only about 17,000 gates," said Hakewill.
Using the 0.18-micron CL018 process technology of Taiwan Semiconductor Manufacturing Co. Ltd., the Tangent-A4 base core is expected to occupy less than 0.2 square millimeter and to run at 225 MHz from a voltage of 1.62 V while consuming less than 33.75 mW. With an ability to execute just over an instruction per clock cycle, that results in 227 Dhrystone 2.1 Mips of performance.
When standard extensions and interface logic to instruction and data caches are added in, the area is still less than one square millimeter before RAM, and the Tangent-A4 should still clock at above 200 MHz, according to team estimates.
Effort has also been put into the arrangement of the additional multiplier that was introduced in ARC3.0 to help it support DSP applications. Hakewill said ARC had designed a new three-stage pipeline for 16 x 16-bit multiplies and rebalanced the four-stage pipeline used for 24 x 24-bit multiplies, enabling a sustained performance at close to 200 MHz.
"We have one beta site that is preparing to use Tangent-A4 and we expect to have a couple more," Hakewill said.