SAN JOSE, Calif. Hardware/software co-design and co-verification tools are attracting what is probably the most diversified audience of any EDA tool category, although some question whether the offerings should even be classified as EDA. Hardware, software and firmware engineers all have their own ways of using the tools, which appear to be equally adept at the chip and board levels.
While vendor positioning can be confusing, there is a crucial distinction between high-level co-design and co-verification. Mentor Graphics Corp.'s Seamless and Synopsys Inc.'s Eaglei are co-verification tools that let users model portions of a to-be-built ASIC or pc-board with HDL simulation, while running software debugging tools on a fast processor model. They're generally used after hardware/software partitioning.
Co-design tools like CoWare Inc.'s N2C or Cadence Design Systems Inc.'s VCC may allow co-verification but involve a lot more such as the ability to create a high-level specification, run functional simulation and performance modeling, evaluate hardware/software partitioning trade-offs and automatically generate interface hardware and software.
Gary Smith, chief EDA analyst at Dataquest Inc., said that co-verification tools today are primarily solving software problems rather than the hardware problems they were intended to target. In a recent market report, he argued that co-verification tools really belong in the embedded software development tool category, not EDA.
The audience served by co-design and co-verification tools defies easy categorization. For example, Peter Becker, staff engineer for L1 implementation at InterDigital Communications Corp. (King of Prussia, Pa.), works mostly on the hardware side of the fence. He uses CoWare's N2C for system-on-chip (SoC) design.
Meanwhile, Thilo Demmeler, a systems engineer at BMW (Palo Alto, Calif.) is working to integrate Cadence's VCC tool into his company's design environment. Demmeler is not designing ASICs or systems-on-chip; rather, he's investigating "drive-by-wire" automotive architectures consisting of off-the-shelf microcontrollers.
Dave Harris, chief technology officer of design services firm In-System Design Inc. (Boise, Idaho), is a Mentor Seamless user who works with hardware and software development. His company uses Seamless for ASIC design.
And Ray Yock, member of technical staff at Lucent Technologies' Wireless Networks Group (Whippany, N.J.), supports the Synopsys Eaglei co-verification product as an internal CAD applications engineer. He works with both hardware and software developers at Lucent WNG, where Eaglei is used for pc-board design.
Shipping in production for over five years, hardware/software co-verification tools have a longer heritage than their higher-level cousins. They're offered by a number of companies, including Mentor, Synopsys, Cadence, Innoveda Inc., Vast Systems Technology, and Cardtools Systems. Some of those vendors are moving into the co-design space as well.
Seamless has "multiple hundreds" of users and is one of Mentor's most successful products, said Serge Leef, general manager of the SoC verification business unit at Mentor Graphics. Primary application areas, he said, are wireless handsets, basestations, switching and wire networking.
From hard to soft
"Originally we positioned this for hardware designers," Leef said. "As we started to develop the market, we saw more firmware developers getting into the game, and lastly we saw software developers using the product." The latter are the fastest-growing group, but more of the users are still on the hardware side, he said.
It's much the same story at Synopsys, were Eaglei has its strongest user base in the telecom industry. "The initial adopters tend to be hardware engineers," said Jay Hopkins, senior technical marketing manager for the Eaglei group at Synopsys. "As we get follow-on and secondary sales, that's when it goes into the software group."
At In-System Design, Mentor's Seamless was recently evaluated on a 500,000-gate SoC printer controller and is now being used as part of the production flow, said CTO Harris. "Our view of Seamless is that it primarily assists the firmware designers in developing their drivers and getting the operating system ported into the target hardware in advance of having real silicon," he said.
The tool is too slow to do a lot of hardware verification, Harris said. But he noted that Seamless is used by hardware developers to look for "corner cases" that arise when the device drivers are integrated with hardware.
One good feature of Seamless, he noted, is the ability to dynamically change the amount of simulation that has to be done on the hardware simulator. Many memory transactions can stay on the software side, which runs much faster, Harris said.
In-System Design has been able to run "hundreds and hundreds of kbytes" of I/O data through Seamless on the software side, Harris said. "You can look at timeouts, interrupt latency, task switching. Basically, you can probe the depths of hardware/software interaction."
Right now, he said, Seamless is mainly used to ensure the OS will boot. In the future, In-System Design wants to do more device driver and low-level software development using the tool.
The value of Seamless is not so much speeding hardware verification as allowing firmware development to start much earlier, Harris said. "We think that on a project with the same number of engineers, we can cut the overall schedule by 30 percent."
Harris hopes Mentor will port Seamless to Linux. Beyond that, he said, "it's really met our expectations of how a tool should perform."
Faster integration BR
At Lucent WNG, Yock worked closely with both hardware and software designers to bring Eaglei into production use. It's gone through evaluation and is being used now to design a board for a time-division multiple-access (TDMA) basestation. Lucent WNG is using Synopsys' Crosslink modeling package for the Motorola 8260 microcontroller used on the board. Crosslink combines an instruction set model with hardware-modeling support for 8260 peripherals.
Eaglei has been a success story at Lucent WNG, Yock said. "It allows us to get to hardware and software integration a lot sooner than we'd normally be able to do."
He said that Eaglei is used after hardware/software partitioning and that it is used by both hardware and software developers, but "more so [by] the software people."
Eaglei acts as a debug environment and adds the ability to integrate hardware and software before there's a real board. The missing hardware can be modeled in VHDL.
"We actually have software sitting on the shelf, debugged with this environment, that's waiting for the real boards," Yock said. "The biggest measure of success is that people want to use it [Eaglei] on the next board."
There are benefits for hardware designers as well, Yock said. "You can use the simulation model as a kind of logic analyzer and probe nets you really couldn't reach on a real board. If you look at it from a hardware simulation point of view, you're gaining speed and better feedback. Trying to look at waveforms and translate hexadecimal data is difficult."
Lucent WNG runs Eaglei with Mentor Graphics' ModelSim VHDL simulator. Yock observed that designers can either run it in "lock step" with the VHDL simulator or in "uncoupled" mode, wherein ModelSim is called only when the software needs to execute a bus cycle.
Yock would like to see additional Crosslink models, including one for Lucent's 16410 DSP. He said he'd like to see a few "minor" improvements in the graphical user interface. "But really, I have no complaints," he said. "It's been very successful for us."
The CoWare N2C and Cadence VCC tools offer co-verification or links to it, but their real focus is elsewhere. N2C lets users enter a C language specification, run functional simulation, map function to architecture, choose a processor support package (PSP) and do software/hardware partitioning. "Interface synthesis" generates driver software and interface hardware, and register-transfer-level C (RTC) is automatically translated to synthesizable HDL code.
VCC also lets users enter a specification and model function, or behavior, separately from architecture. It emphasizes performance modeling and software estimation techniques, which are used to analyze hardware/software trade-offs, bus and processor loading, and RTOS scheduling. It offers interface "refinement" and links to HDL code.
Pete Hardee, director of product marketing at CoWare, said N2C is being used today by a number of leading wireless and consumer electronics companies. "I would say the bulk of our customers are doing hardware design and system integration," he said. "Typically the algorithmic exploration is in Matlab or wherever, and they bring that into CoWare."
Frank Shirrmeister, director of product marketing for co-design technology at Cadence, said that VCC started shipping in production this year and that it is used largely in telecom and automotive industries. He said the most typical users are systems designers and silicon intellectual-property (IP) providers. VCC generally targets a higher level of abstraction than N2C and has stronger performance-modeling capabilities.
At InterDigital Communications, N2C is helping with third-generation cellular systems-on-chip. Becker said that the methodology was proven earlier this year on a pilot project with a Viterbi decoder and that the company is now implementing all of its time-division duplex algorithms in N2C.
"With CoWare, we can dynamically use the same C testbench to drive the high-level and low-level models," he said. "That allows us to dynamically change the parameter sets we're testing against."
To use N2C, Becker starts with untimed C at the highest level of abstraction. That is refined into what CoWare calls a bus-cycle accurate shell model and, from there, into RTC, which is translated into VHDL or Verilog. Becker makes use of the tool's block diagram capabilities. "Since the C language is used for both hardware and software, it's more natural to connect the blocks together," he said.
Becker noted that the block diagram maintains functional partitioning, as opposed to putting all the hardware on one side and all the software on another. That makes it easier to explore trade-offs, he said.
He uses functional simulation to verify the design independently of the processor and then turns to performance modeling after the PSP is selected. Only then, Becker said, is it possible to validate the execution of code on an instruction set processor.
N2C is an interactive tool; it doesn't magically transform a C language specification into RTL VHDL or Verilog. With RTC, you're writing RTL code. "If you code in the same basic style in which you code your RTL VHDL or Verilog, you're going to get code that synthesizes the same," Becker said. C is not as good as VHDL or Verilog for pure hardware design, he noted, but it's better at describing hardware and software from a systems perspective.
Becker uses interface synthesis but noted that N2C needs to mature on the "software" side, which generates device drivers. He'd also like to see support for more processors.
BMW's Demmeler is not using VCC in a production flow today. Instead, he's working in an "implementation and development" phase to fulfill BMW's requirements for the tool. His group is designing networks of electronic control units (ECUs), each generally based around a single microcontroller and peripheral hardware.
"Our goal is that VCC will be a virtual platform," Demmeler said. "We want to distribute functionality onto architecture and optimize this architecture in a very early development step, much earlier than we do at the moment. Then we want to run real-time performance models so we can uncover problems very early."
BMW does not plan to enter a specification or define behavior with VCC. The functional specification at BMW is developed with Ascet/SD, a graphical tool from German company Etas that supports the implementation flow onto a single ECU.
Demmeler said BMW would like to read the Ascet/SD specifications into VCC and do the architectural development work with the Cadence tool. An Ascet interface is one of BMW's requirements.
BMW would also like to run performance modeling, Demmeler said. That would make it possible to gauge the performance of various devices and to model how the ECUs will work together.
To do that, however, Demmeler needs models, which he expects the silicon vendors will provide. "We don't have a ready-to-use library yet," he said. "We are in the startup phase."
Cadence needs to improve the accuracy of its software estimation if it is to be truly usable for BMW's purposes, Demmeler said. On the other hand, he doesn't want to have to spend a lot of time building complex performance models. "The goal is to find a good trade-off," he said.
Another improvement VCC needs in order to support truly complex systems, Demmeler said, is an ability to reuse mapping tables.
Since his group is not building ASICs, Demmeler is not seeking a link to VHDL or Verilog, but the design needs to get into silicon somehow. "One idea would be to export the new design to Ascet/SD and create the link that way," he said. "Ascet/SD has the ability to create software code that runs at the implementation level, and it builds the glue down to the operating system."
If his wish list can be fulfilled, Demmeler believes that VCC will allow "a significant reduction in development time." And that's the bottom line for all the diverse users of co-design and co-verification tools.
A detailed interview with Peter Becker of InterDigital Communications is available at www.EEdesign.com.