Bernd Koenemann feels as though his life's work in testing chips has come full circle. "What's happening now is the chips themselves have reached a critical level of complexity, with many system-level features. And we're at another one of those inflection points," said Koenemann, a senior technical staff member of IBM's Test Design Automation organization.
Koenemann envisions the rise of what IBM has dubbed SmartBIST, first unveiled at this year's International Test Conference, the same venue where in 1979, Koenemann unveiled BILBO (built-in logic block observer).
Whereas conventional built-in self-test (BIST), like its predecessor BILBO, uses a random-pattern generator-which is more "pseudo-random," since it's repeatable-SmartBIST doesn't let the pseudo-pattern generator run free. Instead, SmartBIST makes the tester stay connected to the pattern generator, and nudges it in a more productive direction. That is, SmartBIST modifies the sequence so that the final sequence is customized for a particular test problem.
With today's system-on-chip (SoC) designs approaching 40 million gates, the pressure is now on test companies. The data volume required to test such products is rising exponentially, and the industry is getting to a point where space on standard buffers will become a rare commodity. SmartBIST reduces I/O data volume by up to 10 times, and IBM feels it will work for the next three technology generations: "After that, I hope to be close to retiring, so that it's somebody else's problem," Koenemann joked.
Koenemann has been involved in the test industry for 22 years. He began his career with a four-year stint at Honeywell, before being lured away by IBM in 1984.
But it was the work that Koenemann did in his home country of Germany, as a researcher in the late 1970s, that defined the pace and tone of his career, and perhaps, helped define the last 20 years of the test industry as well.
"Basically, like everything else in this industry, to really tell the story, you can't only look forward, but you must also look back," Koenemann said. As a young man fresh out of university, Koenemann helped invent an early precursor to BIST, a technology that continues to gain momentum and draw interest to this day. The technology is often seen as one answer to the rising cost of "big iron" automated test equipment, and figures heavily in the next-generation ATE-vendor race toward less expensive, more streamlined testers. Built-in self-testing is basically what it sounds like-a way of designing testers into the chip upfront, so as to reduce the long and convoluted data volumes associated with external testing.
"In Germany, I was involved in a government-funded research project. We invented something there called BILBO-built-in logic block observer. We presented the paper at ITC (International Test Conference) in 1979, and all of the sudden, BIST was on the map. I think the presentation had more of a sociological effect than anything. There comes a certain time when things are just ripe, and somebody has to set a goal, and 1979 apparently was that year for the industry," he said.
After the presentation, IBM, among others, immediately drew up plans to develop in-house logic self-test, mired for years in the increasing data volume and the "pigeon-carrier" pace with which that data was transmitted over serial interfaces. Four years later, Koenemann found himself at IBM, involved in the development of the first large-scale mainframe computer that used logic BIST. "So in 1984," he reflected, "I was, in a sense, back to where I started."
|Bernd Koenemann thinks that we are at another inflection point in chip complexity and need to reapply known test techniques smartly inside ICs. |
Primarily in systems houses like IBM, large data processing had reached a level of complexity that testers of the time couldn't handle. "The data volume got out of hand," he said. "That's why BIST was so attractive to IBM. It eliminated all of the binary data from the ATPG (automatic test pattern generator). We set up a task force to look at ATPG, since the run-times were through the roof, and we couldn't handle large enough circuits."
Koenemann urged the industry to unify through simplicity. "The industry needs cooperation," he said. "There is a call in the industry for DFT (design-for-test)-based testers or low-cost testers. And this new, simplified brand of DFT tester, I'm sure, will replace a lot of the current machines.
"Koenemann hopes the test industry will produce a multichip parallel tester. A standalone memory tester can test 64 DRAM chips in parallel, but once you embed DRAM onto a SoC, only one chip at a time can be tested. "Testing that DRAM can be more expensive than making it," Koenemann said. "I think in two or three years, you'll see some practical proposals for parallel testing."
Koenemann also advocates strengthening ties between the design and test camps, which are on the opposite ends of the chip spectrum. The challenge is more organizational than technical, he said. "Designers have to accept that their chip will be modified. And the impact from those modifications must be anticipated up front, which definitely requires acceptance from the design community.
"A similar gap develops regarding the information between design and manufacturing. Memory BIST engines are more complex now, and how will a test engineer know how to operate it? All of the information has to make its way from the design camp to manufacturing.
As the new millennium brings to fruition and fully realizes the impact of Koenemann's 20-year-old research, he couldn't be happier. "Is this the new millennium, or was last year's New Year the new millennium?" he joked. "Who cares? Let's celebrate twice!" At least in a BIST-sense, Koenemann can celebrate once again.