Back when system-on-chip (SoC) designs were new and exotic, designers muddled through with complex, custom-designed hardware and software to do test and debug. Today, as SoC designs move toward mainstream use, demand is skyrocketing for more convenient ways to wring the bugs out. A recent EE Times survey revealed that 30 percent of designers are involved with SoC cores and face the same dilemma they did in the early days of SoC designs: How do you perform test, verification and debug as on-chip cores and function blocks move further away from the chip's external pins?
Designers can't always depend on providers of intellectual property (IP) on those cores to solve their test and debug problems. Many refuse to deliver source code to users, who in turn are hampered in simulation and testing. In effect, what they have bought is a black box. In contrast, many IP core providers happily provide a set of test vectors, leaving the end user challenged as to what to do with the vectors. What's needed is a standard test bus for all cores.
Another major problem with SoC designs is that many of the control and bus signals of interest lie behind the physical pins of the device and therefore are inaccessible to traditional instrumentation such as logic analyzers and in-circuit emulators. Consequently, any tool that depends on access to the physical pins for measurement or test functions is severely disadvantaged. Verifying the operation of first prototype silicon inevitably becomes problematic and creates many hardware and software integration roadblocks.
Synopsys' Rohit Kapur and R. Chandramouli want a core test spec with interoperability between new and legacy designs.
Several articles in this week's section explore the standard on-chip buses under development that allow SoC designers more access to SoC function blocks. Other topics target on-chip debug circuitry issues and the challenges of testing embedded memory on SoC designs.
Both the Virtual Socket Interface Alliance and IEEE are working toward a core test-access standard. And, according to contributors Rohit Kapur, principal engineer, and R. Chandramouli, product line manager at Synopsys' Test Automation Group (Mountain View, Calif.), such a standard must consider not only the interoperability of cores incorporating the standard, but also the existence of non-standard/legacy cores on an SoC. In their article, they discuss the issues of the core test language (CTL), one aspect of the IEEE core test-access standard under development.
At an even higher level is the IEEE standardization effort called P1500, intended as an IP test-access architecture that isolates the IP from the rest of the chip when a manufacturing test is performed. Part of that effort involves the IP test description language CTL. Basically,CTL describes the IP test structure and test operation. The test-access structure consists of wrappers that are logic structures and go around the IP that support both isolation and access test operation.
Improved IC debug
Aside from standards, effective SoC debug requires on-chip debug circuitry. That idea is far from new. For years, Motorola, for example, embedded debug circuitry into its 32-bit microcontrollers. Many SoC cores today provide JTAG interface for debug functions. A few cores at the high end of the performance range are also addressing the issue of providing trace capability, usually in the form of internal trace resources or special buses. These efforts recognize the benefits of real-time execution and bus trace to improve debug. They often fall short, however, when used with multiple cores and complex application-specific IP.
Startup, First Silicon Solutions (Portland, Ore.) recently became the first company to offer on-chip debugging circuitry as an IP core. The company's on-chip instrumentation technology consists of debug block logic integrated into the synthesizable Verilog or VHDL core model. Chuck Swartley, director of marketing and Rick Leatherman, president, explain how the debug block offers a more robust feature set than traditional tools, is nonintrusive and runs at real-time processor speeds.