Despite an industry downturn, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) is pushing forward aggressively with its 12-inch transition program and has laid out a blueprint for six new 12-inch wafer fabs in Taiwan.
It has been a challenging road, said Tsai Nun-sian, the senior director of TSMC's 12-inch project. Tsai talked with EE Times in Tainan about the problems his engineers have tackled during the transition. Here are edited excerpts from that interview.
EE Times: How would you compare this transition, and the problems associated with it, to the one from 6- to 8-inch wafers?
Tsai: If I compare the current status to Taiwan's first 8-inch line in 1993, the speed of maturity and the tool improvement are really much, much faster than the previous generation. In general, the tool uptime or downtime is already comparable with 8-inch production. Of course, we still encounter problems, but the reason I have problems now is because the quantity is smaller. If I had bigger volumes, then I would have fewer problems. Even so, there are still a couple of areas that I feel are behind the others. The single biggest bottleneck is probably the photo area.
EET: What specific problems are you having?
Tsai: There are two problems and both are significant. The first problem is the tool maturity the hardware itself. The second is the system, which includes the software that controls every part that is moving the reticle, the light exposure, the wafer alignment. It's not as mature, so the throughput is far from close to that of its 8-inch counterpart.
In regard to tool maturity, this is my supplier's first system. They have shipped only six or seven in the world, and I have three of them. The majority of the problems are software-related. They have very complicated software and we still need to remove the bugs. In different running situations, we will have different warnings that cause the system to go down. And we need to accumulate enough warnings from this reason or enough warnings from that reason and then go back to look at the source in the software to change it, so in the next batch we can get greater throughput.
This is a continuous process because the photo equipment is a multi-ton body that is moving about one or two meters a second, so the software has to be written in a very conservative way. Otherwise you'll run into a situation where you destroy everything [from a collision], and we won't have a system and they don't have a replacement system.
So the software is written conservatively, then we have to test changes maybe a thousand times before we can relax one parameter and see how it works with another to increase throughput.
EET: Does it matter which geometry you are shooting?
Tsai: I think these photo problems are regardless of the geometry. You might have more problems [with 0.13-micron over 0.18-micron], but usually if you have a software problem it's going to be the same.
EET: What is the second lithography problem you mentioned?
Tsai: It's a process problem for 0.13. I think you will have a higher rework rate. To meet the specification and get a good yield on every corner of the wafer is more difficult. So we will have more problems in that area, which we haven't solved yet. We have finished 0.18 and are in a small-volume running situation. We just started the pilot a little while ago on our 0.13 and 0.15.
Right now, every day, we encounter new problems as we move to new stages. So we are in a debugging phase. The photo, again, is definitely the bottleneck but we just need to keep trying. This is a time of refinement pretty much for the whole industry.
EET: ASM Lithography NV has said it has delivered test versions of its 193-nanometer scanners to you. When do you expect to have versions for use in your 300-mm facility?
Tsai: Up to now, we only have 200-mm systems one in Fab 6 [in Tainan] and two in Hsinchu. They are being used to do 0.13 micron. Their first 193-nm, 12-inch scanners won't be available until the third quarter, but we will definitely want the first ones in our hands. .
EET: In December, at ISS-Taiwan, you said that price parity between 8-inch and 12-inch wafers would arrive sometime next year. Are you still on track with that prediction?
Tsai: I feel even more strongly about it now. If you look at total wafer price, the substrate wafer price will never get parity. Right now it is seven or eight times higher, and it will probably come down to three to four times higher in two or three years.
But when you look at the wafer manufacturing cost, I think we are looking at parity by the end of 2002. We will have a manufacturing cost that is 2.25 times more on 12-inch rather than 8-inch. But that's only one part of the story. The other part is the yield: When you have 100 gross dice on one wafer and on the other you have 225 gross dice. We believe that toward the end of this year we will have this chip probe yield parity across the board. And next year on 0.18, 0.15 and 0.13 we believe we will have higher yield on the 12-inch.
So in 2002, on the one hand, you will get your wafer-manufacturing cost per unit of silicon area to be the same between the two wafer sizes, and then you will have more good dice on 12-inch. So I feel strongly that in the year 2002 you will have much better die cost on the 12-inch than on 8-inch. And in 2003, you are definitely on the winning side with 12-inch. That is why TSMC's strategy is that we don't want to delay or stop anything on the 12-inch transition. If we have to cut down because of slow business, we will cut down on 8-inch.