LONDON Pact Corp. (Munich, Germany), developer of a giant chip that includes 128 proprietary 32-bit processor cores but measures 2 centimeters on a side, will offer a $20,000 simulator for its parallel-processing architecture.
The simulation tool works independently of the number of processor elements on the company's Extreme Processor XPU-128 die, "so you can check how system performance scales," said Eckhardt Bihler, chief executive of startup Pact since February. "It has a graphical interface providing access to the die so you can debug code as it would run on the die." At present that code has to be expressed in Pact's native mapping language (NML).
The XPU-128 processor is intended only as a demonstration vehicle of the parallel-processing architecture, and Pact does not intend to take it into production. The company claims a raw performance of 12.8 billion multiply-accumulate operations per second for the XPU-128 based on a 100-MHz clock frequency.
Although a slight bond-pad problem with the original silicon limited clock frequency to about 50 MHz, Bihler said there was no intention to re-spin the silicon. "This is a proof of the concept. The die is much too large for commercial yielding. It only yields at about 15 percent. But we have die for a few people who want to investigate the architecture and perhaps license it."
The chip also has a prototype C-language compiler that Bihler said will help it be designed into basestations and other wireless-infrastructure applications.
"We have made major progress on the C compiler and can compile small routines in C down to NML," Bihler said. "The compiler can analyze C code for parallelism and then compile to NML. Other code that can't be parallelized is kept in C and is usually sent to a host processor. That's the way the architecture is generally being deployed; as coprocessing support to a host processor."
Bihler said the company was on target to complete compiler developments within six months and was beginning negotiations to put the compiler into the hands of a third party to sell and support. Bihler said Pact had held talks with ACE Associated Compilers Experts BV, but that no deal had been completed yet. ACE (Amsterdam, Netherlands) is working on applying its retargettable Cosy compiler to the Rubicon multiprocessor architecture from Siroyan Ltd. (Reading, England).
Apparently the $20,000 price tag on what is essentially a sales aid has not been a problem for Pact's early evaluators.
"We're talking to several OEMs who intend to test the architecture," said Bihler. "This is not a lot to pay when you're making a major architectural decision." The wireless-infrastructure business is a primary application area for the XPU architecture and Pact is talking to several prominent companies in that area, he said.
Pact is also talking to a few semiconductor device vendors, but getting acceptance from one or more OEMs is an essential part of Pact's strategy for licensing XPU technology to the chip makers, Bihler said.