KYOTO, Japan Intel Corp. researchers have provided a peek at a transistor with a gate length measuring just 20 nanometers, which Intel expects to put into production in 2007 when its microprocessors hold a billion transistors and hit speeds of 20 GHz.
Intel has implemented a 20-nm NMOS transistor but has yet to make a PMOS version, which would be needed to create CMOS circuits. But the transistor indicates the scalability of planar CMOS in terms of transistor size, voltage and speed.
In a keynote speech delivered Sunday (June 10) at the Silicon Nanoelectronics workshop here, Robert Chau, director of transistor research at Intel's components research group in Hillsboro, Ore., cited Intel's belief that planar CMOS transistors will carry it through the rest of this decade. Other chip makers, most visibly IBM Microelectronics, have argued that performance gains from CMOS scaling are slowing, which will require a shift to silicon on insulator (SOI), to strained silicon, or perhaps to double-gated device structures. But Intel has publicly rejected those approaches and said they will be unnecessary for the foreseeable future.
"Planar CMOS will be the standard, but within that basic structure will be a lot of materials changes that are really very exciting," Chau said. "We have many research projects into alternatives, but when it comes to manufacturing chips with one or two billion transistors making those chips in an economical way in a volume manufacturing process then planar CMOS will continue at least through the end of this decade."
The semiconductor industry confronts plenty of technical challenges within the purview of planar CMOS, including the move to lower-k intermetal dielectric materials, the replacement of silicon dioxide with a high-k gate oxide, and a probable switch from a polysilicon gate electrode to a metal gate. Companies will differentiate themselves by their success at implementing a winning recipe, Chau said.
A 30 percent shrink in transistor size will bring a 30 percent gain in transistor performance, without resorting to more complex processes or device structures, Chau said. Equally important is a less-often-discussed historical trend the halving of the cost per transistor with each new technology generation.
At last year's International Electron Devices Meeting in San Francisco, Intel presented a transistor with a gate length of 30 nanometers. That transistor will be used in the 0.065-micron (65-nanometer) technology node, which is expected to come into manufacturing in 2005, according to the International Technology Roadmap for Semiconductors. The transistor with a 20-nm gate length discussed at the Nanoelectronics Workshop corresponds to the 45-nm technology node, which is expected to go into volume manufacturing in 2007. By then, extreme ultraviolet lithography could be used along with 157-nm optical lithography tools, Chau said.
At the Kyoto workshop, Chau updated Intel's progress on the 30-nm transistor. The gate oxide thickness of the transistor is 8 angstroms, or roughly three atomic layers of silicon dioxide between the polysilicon gate electrode and the silicon channel. Gate leakage is an "acceptable" 1.9 microfarads per square centimeter.
The 30-nm gate length NMOS transistors considered the more difficult to create than PMOS transistor, and more commonly used on a chip operate with a 0.85-picosecond gate delay with an operating voltage of 0.85 V.
The PMOS transistor had a gate delay of 1.7 picoseconds. Intel claims that the integrated NMOS and PMOS devices are the smallest reported to date.
Gerald Marcyk, director of components research at Intel's Hillsboro facility, said Intel is sticking by its decision not to implement SOI, having concluded that the advantages in power consumption and speed diminish over time, and are outweighed by higher wafer costs.
"We continue to have an open mind about all these kinds of things," Marcyk said. "I've asked our researchers to go back and take yet another look. But the way we feel now is that as you go from research to development to manufacturing on 300-mm wafers, the slight advantages do not justify the higher costs."
Chau said that Intel's work on junction engineering is another way it has managed to extend planar CMOS without resorting to expensive, complex processes.
"Some companies may have a need for these niche processes, such as SOI," Chau said. "But they introduce a lot of extra process steps. We are moving to 12-inch [wafers]. Just go out and ask the wafer suppliers if they can supply 12-inch SOI wafers in volumes."