SAN MATEO, Calif. Silicon Access Networks will release the first of its networking chips next week, but the iAP address processor will be built on custom SRAM, not the embedded DRAM technology on which the company was founded.
Silicon Access had intended to use its homegrown embedded DRAM extensively in its network processors and coprocessors, but because the company was unable to enlist foundries to apply the technology, it abandoned that idea last year.
"It became clear that the embedded DRAM process wouldn't be supported by the existing foundries," said Mitch Kahn, vice president of marketing at Silicon Access (San Jose, Calif.). "Embedded DRAM has turned out to be very difficult to manufacture."
However, at 0.13-micron line widths, SRAM becomes viable for many of the functions Silicon Access was considering. As a result, the company dropped embedded DRAM and instead designed its own on-chip SRAM.
The SRAM is built on a 0.13-micron logic process from Taiwan Semiconductor Manufacturing Co. Ltd. Borrowing concepts of redundancy that had been applied to its DRAMs, Silicon Access managed to build an SRAM more dense than those available on the market and can accommodate it in a larger die size than usual, Kahn said.
The iAP is the first of five chips that Silicon Access hopes to produce, covering router functions such as packet processing and classification. An address lookup chip, the iAP sits between the framer and the switch fabric, handling address queries.
Most high-end routers use CAMs to handle address lookup, but the iAP relies on tree-search algorithms executed in hardware for its processing. This approach, combined with the use of on-chip SRAM, gives the chip the ability to uncover more data per search, including the address that's required. CAMs, by contrast, return only the existence of a table-address match and require extra searches into associated memory to collect more information.
Silicon Access is developing its own CAMs, but for use in different devices. "CAMs are the right solution for certain problems. When we introduce the iFlow classifier, that has an embedded CAM on it," Kahn said.
The iAP also uses error-correcting code, an additional bit that allows the chip to find and correct errors in data retrieval. Large carriers require it for all memories, Kahn said.
The iAP is a look-aside processor, meaning it doesn't sit directly in the data path. It can handle 64 operations concurrently and process up to 65 million lookups per second, Silicon Access officials said.
Next, Silicon Access will debut a packet classifier and an accounting and statistics chip, both due to be announced later this quarter. The company's packet processor the device often referred to as a network processor is due for release in the fourth quarter, and a traffic manager is scheduled for the second quarter of 2002.