The electrical performance and packaging density of circuits contained in modern high-speed electronic products has reached a point where virtually all integrated circuit package and PCB-level physical interconnects must be engineered at both the electrical and physical levels.
To accomplish this increasingly difficult task requires the coordination of many disciplines. The language used to define the physical characteristics of a working interconnect solution as it is developed are commonly referred to as constraints. These implementation rules can used to constrain the physical design effort to a solution that meets the target electrical performance requirements. Reasonable constraints for interconnect design are rational rules that come from a real understanding of what is important or will make a significant difference. This is interconnect engineering at the physical and electrical level.
Reasonable interconnect constraints are dependent on the noise and timing margins present in a particular circuit. Study the timing or bandwidth requirements to understand what margins exist for signal quality and timing overall. Your margins will help you determine the nature, values and tolerances for your particular constraints.
Digital circuit edge rates do influence constraint development. For example, as edge rates increase, shorter stubs are necessary to keep out unwanted reflections and impedance discontinuities. Stubs are the small variations from a textbook routing topology such as daisy chain, or H tree, that can occur in interconnect routing solutions (see Figure 1).
Stubs are usually undesirable unless they are intentionally used to tune a circuit. The golden rule is "the shorter the better." Long stubs can be the product of: SMD package escape routing, pull up resistors, parallel terminations, and even automated test access points. At 20 GHz, or an edge rate of <50 ps, even the stub formed by a via that extends beyond the layer span of the actual signal conductors involved can be too long, stealing an alarming percentage of the maximum signal bandwidth. Because of this relationship, all (>~1.5 GHz) interconnect-including IC packages-do require complete electrical characterization to ensure performance specifications can be met. Accurate pre-characterization can allow one to take advantage of the longer stubs a straightforward place and route solution imposes.
It is important to include pre-layout physical design studies in your constraint development process. This strategy will help to uncover the differences between the theoretical and more practical aspects of the design and its constraints.. ( A constraint that cannot be physically realized is useless..) Many EDA vendors offer tools for solution space exploration. Solution space exploration helps users determine a set of constraints that meet the electrical requirements at all process tolerance corners.
Constraints for interconnect design come in a variety of types (see Figure 2). Every constraint should be engineered to address a corresponding electrical effect to the degree needed for the particular circuit, with consideration of the cost of its adoption against other alternatives. Going well beyond the degree necessary will only add cost and time, but it does require that you to know the degree necessary. Remember that what is not specified in design constraints is permissible; what is specified might not be physically realizable. Reasonable constraints not only meet the electrical performance objective, but also meet the test of physical attainability.
Some constraints developed in the planning stage of a project in electronic form can be enumerated and input to CAD design automation tools using the internal tool command formats and possibly some scripting effort. A new generation of tools has begun to appear that offer facilities to manage, translate and simplify the passing of constraint information between EDA applications. The capabilities of tools vary a lot in this area.
Constraint Development Scenarios
Examples of reasonable constraint development can be found in a discussion on the interconnect engineering of an LVDS switch fabric design implemented in 16-layer all single-layer strip line and microstrip (outer layers). This particular switch fabric circuit utilizes a heavily loaded 40 MHz system switch control bus between eight telecom switch ASICs and the microprocessor (see Figure 3).
Even at this low a clock rate it can be a very challenging to develop a decent signal quality routing solution from 1 ns edge rates on such loaded lines that can drive in one of six different directions. Floor planning and routing studies-as well as the engineering specifications for device I/Os, package parasitic, noise and timing margins, temperature effects and stack-up definition with tolerances-were considered. All corners were modeled and rigorously simulated to develop the following constraints (see Figures 4 and 5).
The interconnect engineering of the power delivery circuits for the same switch fabric ASICs identified the constraints needed to achieve low noise I/O, Core, PLL and Vref voltage sources. Always consider the silicon manufacturer's layout recommendations. Power delivery constraints are applied down to the pin instance level (see Figure 6).
The final physical routing constraints for the power delivery circuits were based on minimizing parasitic effects, coupling to signals and getting control of the substrate currents (see Figures 7 and 8).
Ten 32-bit 622 Mbit LVDS source synchronous differential switch fabric busses are used to interconnect the telecom switch asics ASICs to one another (see Figure 9). The development of the routing constraints for the 622 Mbit switch fabric required characterizing many differential line and substrate configurations. The relative length variation permitted within each bus A-J and within each pair was constrained to leave suitable margin left for the silicon, IC package and board fabrication process variations.
Typically, these type of circuits require the differential length variation to be within 5% of the signal edge rate. At 622 Mbps this amounts to about 0.100", at 2 Gbps to about 0.025", and at 10 Gbps to only about 0.01". The following physical routing rules for the switch fabric busses were developed after adjusting for loss, noise, temperature, package parasitic and fabrication process corners (see Figures 10 and 11).
Interconnect engineering at the physical and electrical level is needed for modern high-speed IC package and board-level circuit development. Budgeting the time and resources to develop reasonable constraints will reduce the overall development time. There is no "one" set of interconnect constraints that work for a particular circuit. There are many possibilities that can work; unfortunately, time and space does not permit exploring them all. Imperical constraints that worked in the past can be unreasonable when applied to modern interconnect designs.
Bernard Voss is the principle interconnect engineer at the consulting group, SiQual Inc., Tualatin, OR. Voss has been in the interconnect design business for over 18 years, engineering interconnect solutions for hardware development teams worldwide.
Electro Magnetic Compatibility and Printed Circuit Board (PCB) Constraints, Application Note ESG 89001, Philips Semiconductor Corp., June 1989.
High Speed Transmission with LVDS Link Devices, Application Note 1059, National Semiconductor, Susan Poniatosksi, June 1998.
Implementing the Lucent 8206 Bus in Compact PCI Applications, Report #99GC011, AMP Corp., October 19, 1999.
PC-PGA Intel Pentium III Processor and Intel 840 Chipset Design Guide, (c) Intel Corp., January 1999.
High Speed LVDS Clock Distribution Using the DS92CK16 Clock Distribution Device, Application Note AN-1173, National Semiconductor, Milt Schwartz, September 2000.
Managing Constraints Throughout the Design Process
The percentage of nets on a printed circuit board that have high-speed constraints has grown rapidly and dramatically. In 1999 from 10-25% of the nets on a board were constrained; in today's high-speed boards up to 75-80% of nets are constrained. Developing reasonable constraints early in the design process is tricky enough, managing them through the rest of the process is critical to first time success of complex high-speed densities.
Faced with the escalating challenges of timing analysis, signal integrity, crosstalk, power delivery and EMI issues, engineers are becoming painfully aware that managing constraints using manual methods no longer works. Electronic constraint management (ECM) is being recognized across the industry as the only way to handle the rapidly growing number of constraints efficiently and accurately. ECM is the process of crafting, editing and validating design intent in the form of design constraints. Importantly, ECM makes imprinting design rules into the layout system easy. Imprinting is critical to ensuring accomplishment of the current design, as well as providing a successful platform for reuse.
Applications experience indicates that for an ECM system to be effective, it must be integrated throughout the design process, it must be easy to use, and it must include hierarchical management.
Perhaps the most important feature of any electronic constraint management system is its overall integration. To give a design team the flexibility it needs to create, edit, and validate constraints at any point, the constraint management system must be tightly integrated at every point. Pre-layout simulation work needs to be saved in comprehensive rule sets to be applied later on in the design flow. Once a netlist is captured in the schematic tool, an association can be made between the various design elements and rule sets. Integration should include the ability to utilize the DRC, simulation capability, and the ability to display rule status in real-time based on the current state of the design. A design flow can be put together with excellent point tools for each step; however, you might end up with several different GUIs and several different constraints formats, creating time-consuming problems.
A key benefit of a constraint management system is the ability to capture, manage and validate the different rules in a hierarchical fashion. Hierarchical constraint management means that the rules can be grouped together and assigned to design objects (such as nets). This has the advantage that there is now one central place to go to edit those particular rules. Handling constraints as individual properties is cumbersome and time consuming-and is now a thing of the past. Additionally, it should be possible to override a particular constraint on a net on a case-by-case basis as appropriate.
The ability to easily create topologies graphically is another important capability of an ECM system since many semiconductor companies provide physical guidelines-referred to as net topologies-for designers to use when using high-speed chips on a PCB. The flexibility to extract topology from design elements at both the schematic and board layout level, speeds successful design. Additionally, these topologies should contain constraints beyond just the net schedule and the capability to simulate from these same topologies for the purposes of creating and validating constraints.
Using an electronic methodology, constraint management can play a crucial role in successful high-speed designs by limiting the amount of translations and by driving the downstream layout process. The end result is that cycle time is reduced and post layout verification becomes more of a sign off than a costly revision of the design.
Dennis Nagle is a technical marketing manager at Cadence Design Systems Inc.
© 2001 CMP Media Inc.
6/1/01, Issue # 1806, page 26.
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