SAN JOSE, Calif. Companies that want to embed blocks of programmable logic into standard-cell ICs are going to have to go through leading FPGA vendors Altera Corp. and Xilinx Inc., which hold key patents and technologies for programmable logic. That caveat, from John Daane, president and chief executive officer of Altera, could set the stage for a legal showdown as interest in adding programmable logic into otherwise hardwired devices gains momentum.
But Daane's assertion, made during an interview with EE Times, is disputed by some proponents of embedded PLD cores. And work proceeds apace on variations of the embedded-programmable-logic theme.
LSI is working with Ericsson on a broadband communications processor that uses embedded programmable logic. The first prototypes will be manufactured next quarter, said LSI ASIC technical marketing manager Peter Gasperini. Programmable-logic vendor Actel Corp. has also jumped into the embedded PLD fray by making its "embedded programmable gate array" available through some leading foundries.
Meanwhile, eASIC has proposed a repeatable logic fabric that is based on FPGA-like lookup tables but that strips out the local interconnect and is programmed at the mask level. The mask-programmable route, eASIC claims, can enable higher speeds and 30 times better density than bit-stream-programmable logic.
Such developments notwithstanding, Altera's Daane said the broad patent portfolio and software schemes of the two largest PLD vendors poses "a tremendous barrier to entry" for other vendors that want to sprinkle programmable logic into ASICs or standard products.
Altera and Xilinx, which settled a longstanding patent dispute of their own this year, have extensive patent portfolios covering PLD architectures and software schemes for test and repair of programmable logic. The use of programmable-logic structures by providers of application-specific standard products will be "impossible unless they work with ourselves or Xilinx to license the technology," Daane said.
As evidence, he noted that ASIC vendor LSI Logic Corp.'s two-year-old program to integrate programmable logic into an ASIC flow has resulted thus far in just one announced device, which has yet to be manufactured. Daane spent 15 years at LSI Logic, most recently as executive vice president for communications, computer and ASIC products, before being hired last year to take the helm at Altera.
Not surprisingly, those with a big stake in embedded programmable logic take issue with Daane's assertions. Adaptive Silicon, which has designed special PLD structure that can be wedged between standard logic on the same chip, argues that its arithmetic logic unit (ALU)-based programmable logic structure is different enough from traditional, lookup table-based FPGAs to escape scrutiny. The company has obtained two patents so far and does not consider it necessary to reach cross-licensing agreements with the major PLD vendors.
In fact, LSI Logic licensed Adaptive's technology under Daane's watch. "He was at LSI Logic when LSI did considerable due diligence before licensing our technology," said Ralph Zak, vice president of marketing for Adaptive Silicon (Los Gatos, Calif.). "We believe they would not have proceeded unless we were fairly clean from a patent portfolio standpoint."
LSI Logic's Gasperini, who oversees its embedded PLD line, said he believes Adaptive's architecture is distinct from other PLD vendors and that customers have not expressed concern about patent issues. From LSI's standpoint, the real work that needs to be done is developing the tools and design flows that can mesh with its ASIC design methodology, a painstaking effort that involves file exchanges, timing closure, power analysis and test insertion. That process is "99 percent done," Gasperini said.
Indeed, that is why it has taken more than two years for LSI to come out with the first product using embedded PLDs. "With all due respect to [Altera's Daane], I think he's missed the point," Gasperini said. "He's right in that you have to have the right portfolio for reprogrammable intellectual property, but that's just the first step in a very long series of steps."
While handcrafting custom circuits will remain common for those companies that can ship in very high volumes, there is a need for a more coarse-grained logic fabric for designers worried about development costs. That need is becoming more acute as the cost of making a mask reaches $700,000 or more at the 0.13-micron process node, said Zvi Or-Bach, president and chief executive of eASIC. "With NREs [nonrecurring engineering costs] at $3 million, you need to generate $10 million from the silicon," Or-Bach said. "This is creating barriers for using 0.13 micron."
Or-Bach's company will announce next week it has achieved logic speeds similar to standard-cell speeds by tapping phase-shift mask technology to reduce the transistor poly gate length to 0.07 micron using 0.13-micron design rules. The phase-shifting technology, which is being implemented at foundry United Microelectronics Corp., was developed by Numerical Technologies Inc.
Concerns over NRE costs have also sparked interest in embedded programmable logic. In some cases, it may make sense to give up some density in order to spin a single chip that can be tailored for different applications through programmable logic cores, proponents argue.
"What's driving a lot of discussion is the increasing costs of masks for different variations of the chip," said Adaptive's Zak.
Altera and Xilinx, for their part, are coming at the issue from another direction, promoting the use of cores in conjunction with their programmable-logic fabrics. That includes the software tools.
For example, Altera recently said it would integrate MathWorks' Simulink digital signal processor design tool into the Altera Quartus II development software, a move that it said would provide a PLD methodology similar to methodologies that are already familiar to DSP engineers.
Meanwhile, Xilinx officials indicated recently that the company would consider licensing its FPGA technology, but thus far it has not announced any deals. Daane said that there have been discussions about doing so at Altera but that right now the company is more interested in pursuing its "system on a programmable chip."
No lack of interest
Altera's hesitance to license its technology, however, is not due to lack of interest, Daane claimed. "We've been contacted by just about every ASSP company out there," he said.
One company considering embedded programmable logic is Artile Microsystems Inc. (San Jose), a subsidiary of Toshiba America Electronics Components that builds system-on-chip processors.
"It is feasible technology-wise; it's also costly," said Jim Smith, Artile's director of business development. "In the spaces we're going after, such as high-volume set-top boxes, it may not be the best way to go. But in areas like communications, where the standards are changing and you may need to accommodate changes more rapidly, then programmable logic may have a place."
More details of programmable logic vendors' plans to expand into systems-on-chip will come to light in San Jose next month at the Microprocessor Forum. Announcements will include disclosures on a Xilinx PowerPC core codeveloped with IBM Microelectronics and a QuickLogic MIPS-based embedded processor with programmable logic.
The tendency for PLD vendors to pack more intellectual property into their devices affects not only their approach to design but also the way PLD vendors work with their customers. As PLD vendors move deeper into the system-on-chip realm, they are finding that they must reach out to more top-level engineers that have a handle on system partitioning.
"You need to really talk to the system architects, not just the engineers," said Daane. "We are becoming a big part of the bill of materials for those systems."