SAN MATEO, Calif. Altera Corp. and Xilinx Inc. are hoping a slew of new processor cores will draw more system architects to choose programmable-logic devices over ASICs. The cores represent one of the most intense battles between the two top PLD vendors as they jostle for leadership in the high end.
Leveraging both homegrown and third-party processors, the companies say they expect to play a greater role in applications like networking, where hard- and soft-processor cores can work in tandem. As they reach out to system architects, it's becoming increasingly important for PLD vendors to provide customers with a way to partition hardware and software.
"We're seeing a large number of customers that are interested in having control functions on the FPGA rather than on the side," said Babak Hedayati, senior director of product marketing at Xilinx. "They'd prefer to offload some functionality on the controller rather than do everything in logic."
Indeed, Altera, which got the ball rolling last year with its Nios soft-processor core, said it has shipped 2,500 Nios development kits to paying customers and expects to train 3,000 customers by year's end.
"We realized that it's not about the instruction set. It's about how easy it is to use and put the systems together and compile down," said Jordan Plofsky, senior vice president of embedded-processor products at Altera.
Altera this week announced its second spin of the Nios architecture, available in 16- and 32-bit versions. The core is smaller and faster than the earlier Nios, and includes new features like arbitration logic to support multiple processors and customized instructions, the company said.
At the same time, Altera rolled out its ARM9-based Excalibur, which will come in three versions with different amounts of programmable-logic array and SRAM. Based on a hard-processor core, the device will serve as Altera's high-end processor solution for the foreseeable future.
Xilinx, for its part, is offering its Microblaze processor core, which runs as high as 125 MHz, making it the leader in raw performance, according to the company. The processor is geared for IBM's Coreconnect, a freely licensable on-chip bus that will serve as the common link for the company's cores. Xilinx is also planning to roll out by early next year a PowerPC-based FPGA device that is slated to run faster than 300 MHz, giving it a performance rating of 420 Dhrystone Mips, according to the company.
Altera modified the Nios core so that it takes up fewer logic elements, the building blocks of its PLD fabric. This reduced the routing overhead, kicking up the speed to 80 MHz and boosting performance to 40 Dhrystone Mips.
As part of the Nios offering, Altera has included arbitration logic that toggles data traffic between the Nios processor bus, known as Avalon, and data memory.
"You can add an unlimited number of masters and we can get gigabit-per-second bandwidth. In communications systems, you can use multiple masters to send and receive packets simultaneously," said Anna Chiang, director of marketing for the Excalibur business unit at Altera.
Another trick is the ability for customers to create up to five new instructions that are translated into hardwired logic. By exploiting this feature, a user can see performance improve by as much as 75 times, depending on the application and the regularity of the code, according to Altera.
Xilinx, for its part, is emphasizing the raw performance of its Microblaze core, which became available this week. The fastest version runs at 125 MHz on the company's Virtex 2 FPGA, and has a performance rating of 82 Dhrystone Mips. "What we care about is Dhrystone Mips that's where the processor shows its capabilities," said Hedayati. "We have a tremendous speed advantage."
Microblaze uses a two-tiered bus structure based on IBM's Coreconnect on-chip bus. The soft processor is connected to the local bus, and bridges to an on-chip processor bus from which peripherals hang.
The use of Coreconnect will provide a common link to a forthcoming device with an embedded PowerPC core, licensed from IBM. Xilinx envisions, for example, using two PowerPC cores and five Microblaze processors on one FPGA, all tied together through Coreconnect. The company expects the PowerPC-based device will be ready to ship by early 2002.
Rather than placing it in the corner of the chip, Xilinx is putting the PowerPC core in the middle of the FPGA fabric. Hedayati said this was more of an engineering challenge because it required changes to the software and routing structure, but was necessary for processing data coming in over 3.125-Gbit/s serial I/Os.
Meanwhile, Altera said its first hardened-processor device based on the 200-MHz ARM922T is ready to ship now. Part of Altera's Excalibur family, the device includes single- and dual-ported SRAM, an interface to external SDRAM, a JTAG port and various processor-specific peripherals. By the end of the year, Altera plans to come out with three versions that will have varying amounts of programmable elements and SRAM.
The processor subsystem, which sits on one edge of the chip and takes 11 percent of the die area, can run on its own without setup from the PLD array. Bridges that link the processor, memory and PLD fabric have been preinstalled. Except for the smallest version, the ARM-based devices include a trace module for software debug.
Altera is also keeping an eye out for applications that can use both hard- and soft-processor cores in a PLD. A packet processor that encodes and decodes optical channels, for example, could use two Nios processors and two packet processors in the PLD fabric, and hand off exceptions through a dual-port memory to the ARM processor.