Ken Rygler, an executive vice president at DuPont Photomasks Inc. (Round Rock, Texas), is trying to figure out how to save his customers money. So is John Martin, the chief technology officer at Chartered Semiconductor Ltd., the Singapore-based foundry.
Rygler, a tall man who seems to be constantly in motion, worries that some of his potential customers are choking on rising mask costs. A mask set for a 130-nm (0.13-micron) design can range from $500,000 to $800,000, depending on how much data is involved.
Rygler said DuPont is working with customers to determine mask-level defects that either don't print on the wafer or prove irrelevant to yields.
A perfect mask may deliver a slightly wider process latitude, which is fine for customers willing to spend more to get a better speed-bin sort of the fastest die. "We are getting anecdotal evidence from customers that if it is not a performance-oriented device, there are certain kinds of so-called defects that may not make a difference," Rygler said.
Chartered Semiconductor's Martin, who earlier worked as a process research fellow at International Sematech, has been promoting the idea of a standard foundry process, with the 100-nm process node as the prime target.
By having a common CMOS process as the figurative "motherboard," the foundries and integrated device manufacturers could compete by creating their own "daughterboard" modules that would support analog circuits, silicon germanium or silicon-on-insulator.
Martin argues that most chip manufacturers will converge on one or two low-k materials and that the differences between bulk CMOS process technologies will be minimal at 100 nm. A chip design could be created using a single set of libraries, which could be targeted to the "standard" process.
Chartered may want to become compatible with TSMC's process, and the startup foundries in Malaysia and China certainly would benefit if they could ride on the coattails of TSMC or UMC. However, process technologies diverged markedly in the 130-nm node, and I expect that to increase at 100 nm as some companies choose different gate insulators and intermetal-layer dielectrics.
Since manufacturers use different steppers and resists, different mask sets would need to be created for each manufacturer. But at the least, people are thinking about how to reduce costs, and barriers to entry.
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