STANFORD, Calif. After having downplayed the benefits of silicon-on-insulator transistor technology for years, Intel Corp. now will spin its own version, saying it will address circuit designers' gripes with SOI while retaining the technology's low-power, low-capacitance attributes. At the same time, the company has chosen a high-k gate dielectric to replace silicon dioxide, which many experts believe will become too thin to be effective below the 0.10-micron node.
Intel's decision to use silicon-on-insulator technology comes after five years of study and is considered a key step in reducing transistor leakage and voltages. By implementing its own brand of SOI with high-k gate dielectrics, the company claims it will be able to build transistors that operate at terahertz speeds within the decade, while keeping power consumption in check.
If those changes are not made, Intel predicts, the heat generated by its microprocessors will slope upward exponentially, reaching the power density of a nuclear reactor before 2010.
"My job is to make that flat," said Gerald Marcyk, director of components research at Intel. "There is no fundamental physical problem with making these transistors really small and fast. The problem is, they start to consume too much power."
Intel's move to incorporate new materials in its manufacturing process is part of its multipronged battle with power dissipation. At the circuit level, the company is starting to implement body biasing for a greater range of voltage thresholds. Its architectural engineers, meanwhile, have built in latent-multithreading technology that will be activated in Pentium-4 systems next year, and they're looking into extending the concept for microprocessor cache hierarchy.
At the process technology level, Intel is looking to SOI as one means of keeping power under control without thwarting the move to terahertz transistor-switching speeds. But Intel is putting its own twist on SOI by using a much thinner insulator substrate, which it calls a depleted substrate transistor. More commonly referred to as fully depleted SOI, the technique allows the transistor's source and drain to sit directly above the insulator layer, effectively isolating the silicon body between the source and drain.
By contrast, IBM Microelectronics acknowledged as the pioneer in commercializing SOI technology uses partially depleted SOI, which leaves a sheath of silicon between the insulator at the bottom and the source/drain terminals above.
Marcyk claimed fully depleted SOI offers better junction capacitance, lower off-state leakage, fewer soft errors, lower operating voltages and lower gate delay than the partially depleted variety. Most important, he claimed, it eliminates the so-called floating-body effect associated with conventional SOI, or the tendency for unwanted charge to build up in the transistor body.
The floating-body effect vexes some circuit designers because the threshold voltage starts to depend on earlier states, in a phenomenon known as the history effect.
"I do know some engineers are still worried about the history effect, so there will be some 'show-me' pushback on the process," said Gary Smith, chief EDA analyst at Gartner Dataquest. "Until it's proven, engineers will be cautious."
But IBM fellow Ghavam Shahidi said the history effect has been overblown. "The history effect is less [of an issue] for fully depleted SOI, but it is a very small effect to begin with, and it's hard to measure. I'm not sure why Intel is making it a big deal," he said.
In fact, fully depleted SOI is not necessarily immune from floating-body effects, Shahidi contended. "If the source and drain are high, the body will charge up; that's a condition you see even in fully depleted [SOI]," he said.
Moreover, fully depleted SOI worsens short-channel effects, making it hard to attain multiple threshold voltages. And analog circuits still need to make contact with the body, which can't be done with fully depleted designs.
I think this shows [Intel's] lack of experience," Shahidi said.
Intel did acknowledge that fully depleted SOI creates higher resistance in the source and drain terminals because there is no silicon touching the cobalt-coated terminals. To counteract that effect, the company said, it will grow thicker source and drain regions, thereby lowering the resistance and boosting drive current.
Steeper slope, lower leakage
The one-two punch of fully depleted SOI and raised source/drain regions is claimed to give the transistors a steeper subthreshold slope and much lower off-state leakage than conventional SOI and bulk silicon. Marcyk said partially depleted SOI has a 100x higher off-state figure than fully depleted SOI. Raising the source/drain regions improves drive current 30 percent for a given voltage threshold and given geometry, he said.
"What we're saying is that fully depleted SOI is the right answer, and we think everyone will have to do this in three to five years," Marcyk said.
Going to fully depleted SOI means wafers will have to be capped by layers of silicon as low as 30 nanometers thick, which is less than a third the thickness of partially depleted SOI. Wafer manufacturers' ability to control that ultra-thin layer is a "significant concern," Marcyk acknowledged.
Answering the call
But wafer manufacturer Soitec, which just received a multimillion-dollar order from Advanced Micro Devices Inc. for SOI wafers, claims it is up to the task. "We just announced in July that we can get layers of silicon as thin as 30 nm," said Soitec president Andre Auberton-Herve.
Intel's decision to adopt high-k dielectric material for insertion beneath the transistor gate isn't surprising, since most IC manufacturers are moving in the same direction. High-k dielectric films promise to let chip makers grow a thicker insulation layer to reduce leakage while keeping capacitance constant.
For that purpose, Intel selected zirconium oxide, which has to be built up in single-layer molecules using atomic-layer chemical vapor deposition. The method lets Intel reduce gate leakage by 10,000 times, without any change in capacitance, Marcyk said.
But the jury is still out on high-k dielectrics. Among the questions is the material's ability to withstand high temperatures when the source and drain regions are being doped.
"Zirconium is one of the top materials, but I don't see what makes it stand out yet," said Shahidi of IBM.
Intel said it now has a chemical vapor deposition tool that can handle the high-k material for use with 300-mm wafers. And several equipment vendors are busy working on atomic-layer CVD tools, said Dean Freeman, principal analyst at Gartner Dataquest.
Marcyk said Intel plans to introduce its fully depleted SOI, raised source/drain transistors and high-k gate dielectric materials at different stages in the 90- and 65-nanometer process technology nodes, but he would not disclose the sequence of introduction. Intel expects to move to the 90-nanometer node in 2003 and then to 65 nm in 2005.
Freeman said it may make sense to integrate the high-k dielectric materials first. SOI "is not that difficult to integrate, because you're still processing a standard wafer, but from a device performance standpoint it will probably require more understanding," he said.