Although DRAM pricing has plumbed depths never seen before 2001, researchers have continued to reach for new heights. Recent technology developments in volatile memory, allowing for greater chip density and functionality, are shaping up to make 2002 as interesting from a technical point of view as 2001 was hellish from a business point of view.
The ongoing segmentation of the DRAM industry is expected to intensify over the next three to four years. During that time communications and consumer applications are predicted to take up a much larger slice of the pie, replacing the computer segment as the drivers of new growth.
That is fueling R&D into specialty memories that better suit the specifications of certain applications, such as low-power DRAM for cell phones, personal digital assistants and digital still cameras, or fast-cycle RAM for network processors, routers or set-top boxes.
By 2005, consumer and communications applications will consume 18 percent and 20 percent of the total DRAM market, respectively, up from today's 9 percent and 12 percent, according to Semico Research Corp.
But which flavor of DRAM will work best within each segment is an issue system designers are wrestling with as the industry digests various specs and individual vendors plan their road maps.
"This is really causing difficult design choices for our customers," said Lane Mason, memory market analyst at Denali Software Inc. (Palo Alto, Calif.), a supplier of verification tools and intellectual property to the DRAM industry. "In some cases the specs for something that is 18 months down the road still haven't settled down yet," he said.
A case in point: embedded DRAM. As the semiconductor industry moves toward system-on-chip, embedded DRAM is a technology with unrealized potential. Suffering from a lack of standardization, the memory is still losing out to SRAM in system designs.
"It will get better as the market gets larger on the vendor and ASIC-designer end, and also as the fabrication industry consolidates further," Mason said. "When it gets to be a billion-dollar market instead of a $100 million market, there will be a lot more interest in it and you'll have to have portability to take it from one fab to another, so there will have to be some standard processes that you adopt."
But for now, the three main players IBM, Mitsubishi and NEC all appear to be pursuing their own interests. "I see no move to share in the interest of having a second source. They think that [embedded DRAM] is their family jewel, and it has performance that you can't get anywhere else for certain applications," said Mason.
Industry observers also believe that DRAM arrays with an SRAM interface pseudo SRAMs will start to make gains, coming from companies like Hitachi, Hynix, Samsung and Toshiba. With better performance than a DRAM, yet with similar pricing, it will be 20 to 50 times cheaper on a per-megabyte basis.
On the manufacturing side, other technology challenges await as the industry moves along its traditional cost-reduction curve by shrinking design-process rules. So far, designers and manufacturers have driven down bit cost by quadrupling density every three years. But such transistor-array scaling is quickly reaching its limits.
"You might think that an odd thing because normally, the logic folks have scaled their transistors to tiny dimensions," said Gary Bronner, program manager of the DRAM alliance between IBM Corp. and Infineon Technologies AG. Both companies are working on the development of memory chips at the 0.11-micron generation. At the International Electron Devices Meeting last month, IBM introduced a double-gate vertical transistor that would be built within the trench, a major move in tinkering with the array architecture. "That gives us a path for scaling DRAMs well below a tenth [of a] micron. We think that's a pretty big breakthrough," Bronner said, adding that he believes the new architecture is capable of reaching the .07-micron node using 193-nanometer lithography systems.
IBM and Infineon have taken the concept of the cell and built a 128-Mbit chip on an 0.18-micron process, which has delivered acceptable yields. The team is now shrinking the cell to the 0.1-micron node and is expecting a prototype chip in 2002. The goal is to have it in mass production by the end of 2003.
But Bronner said the vertical-transistor concept conceived for trench use will be hard to adopt at companies that use stacked-capacitor technology. And that is about two-thirds of the industry, including Micron Technology Inc. and Samsung Electronics.
"The stack people will have problems because they can't physically go up forever, so they will have to rely more on high-k dielectrics and the advancement on those has not been great," Bronner said. "So the real question is, how well will the stacked-capacitor companies be able to scale in the future as you get below 0.1 micron. Right now that's still an open question."
At Micron, chief technical officer Mark Durcan said his team is making good progress on scaling stacked capacitors despite the challenges of working with new high-k-dielectric materials.
"It is true that up till now the trench guys might have enjoyed somewhat of an advantage with respect to embedded memory, because they could build an SIS [silicon-insulator-silicon] capacitor down inside the hole and then build the transistor," he said. "And once they built the transistor they didn't have to see very much temperature after that, so they could build a very high-performance transistor. But what's happening with the stack guys is that as we move to MIM [metal-insulator-metal] capacitors, we're getting the performance equivalent to what the trench guys are getting, but we have the option of using high-k dielectrics." Durcan also believes that companies using stacked technology will be able to incorporate vertical transistors into their designs, but probably not until the 0.08-micron node or below. "It's not a fundamental limitation of the stacked capacitor," he said.
Key DRAM technology forecasts can be garnered from the following:
See related chart