SAN ANTONIO, Texas The progress of computer graphics was evident at the annual Siggraph conference and exhibition this week, as computer scientists, designers and researchers presented the latest developments in graphics and interactivity techniques. One company showed 3-D software that could be applied to future chip designs.
The best evidence of progress was sophisticated 3-D software running on PC platforms, rendering volumetric images and manipulating them in real-time. Meanwhile, the Web continues to expand as a delivery mechanism of 3-D images, based on Siggraph demonstrations.
One indicator of industry-wide activity was Intel Corp.'s announcement that it will join the Web3D Consortium, a forum that backs the creation of open standards for Web-based 3-D graphics. Intel also announced the establishment of the CAD 3-D working group under the Web3D umbrella. The group will define, develop and deploy a common format to represent 3-D images on the Web.
The working group expects to complete its initial standards development effort in about 18 months.
The group aims to reduce the time and cost associated with developing and publishing 3-D content for the Web, while providing CAD tool users a more effective means to collaborate and share data for design, marketing and manufacturing applications.
"By working with industry leaders and graphics experts, we plan to create a format that will do for 3-D on the Web what the JPEG format did for digital photography on the desktop," said Pat Gelsinger, Intel's chief technology officer.
There are multiple formats for viewing 3-D content on the Web, which make it difficult for companies to use. The creation of the content is also too costly for many businesses to justify for use on their own Web sites. This has led to a lack of content and has slowed the pace of innovation and adoption of 3-D on the Web. The majority of today's 3-D content is created in CAD applications, so the working group will initially concentrate on providing greater access to that data.
Aside from Intel, the working group includes 3Dlabs, Actify, Adobe Systems, ATI Technologies, Boeing, Dassault Systems, i3Dimensions, Lattice Technology, Microsoft, Mental Images, the Naval Postgraduate School, the National Institute of Standards and Technology, Parallel Graphics, SGDL Systems and Tech Soft.
Meanwhile, startup i3Dimensions Inc., a member of the CAD 3D working group, unveil its first generation of products at Siggraph. The company said its Pixel3 Object Editor and Client is able to import, modify and dynamically manipulate and view complex 3-D models on off-the-shelf PCs or laptop computers.
"i3Dimensions today delivers the first phase of our product development program," said Paul Lindahl, president and chief executive officer of the company, based in Vancouver, British Columbia. "While our initial products are best applied to advancing e-learning and field service applications, we believe our Pixel3 technology will, over time, have major implications for all facets of the 3-D industry."
Lindahl did not rule out applying Pixel3 technology to analyzing and manipulating the physical properties of IC designs to optimize next-generation ICs for optimum manufacturing processes.
Pixel3 is comprised of a 3-D software framework and a real-time volume graphics engine. The software framework provides the infrastructure to assemble and manipulate digital objects. The Pixel3 Object Editor can convert existing 3-D assets or models including laser scans, MRI/CT scans, terrain data, remote sensor data, and CAD models into the Pixel3 file format. Unlike other 3-D technologies, the graphics engine enables users to dynamically update, change and interact with complex and realistic models on common PCs without requiring graphics hardware acceleration.
In effect, users can manipulate 3-D images at 15-to-20-frames/second, and take away graphic layers one by one to reveal the objects that make up a 3-D image, all in real-time. In a hypothetical 3-D representation of an IC design, the technology can be used with an EDA analysis tool to optimize the placement and relocation of interconnects in a chip, for example.