SAN MATEO, Calif. In a move that tightens its grip on the language road map for next-generation IC design and verification, Synopsys Inc. has purchased Co-Design Automation Inc., creator of the Superlog language the only viable competitor to the Synopsys-backed SystemC.
By taking ownership of Superlog, Synopsys now has a hand in controlling the future of register-transfer-level (RTL)-based design in the near term, buying it time to refine its C-based design tool, which it hopes will replace HDL tools as the starting point of IC design. Meanwhile, the company is seeking to appease backers of Superlog by promising to support it as an extension to Verilog and an intermediary step to SystemC.
Synopsys has already said it will continue to promote SystemC for system-level design.
The acquisition a combined stock, options and cash transaction worth $36 million that's expected to close in two weeks also brings Synopsys the SystemSim Superlog simulator and SystemX expander of Co-Design, as well as an all-star R&D team.
Gary Smith, Dataquest's chief EDA analyst, called the acquisition a coup that "gives Synopsys some of the best Verilog R&D engineers around, keeps Cadence from getting some of the best engineers around and silences a critic [Co-Design president and CEO Simon Davidmann] on the Accellera working group."
Accellera is working to integrate most of the constructs of Superlog into the next-generation Verilog language, SystemVerilog. Davidmann had regularly criticized SystemC because, unlike Superlog, it was not an evolutionary step for HDL users. But Davidmann last week said he now believes the two languages are complementary and can coexist.
Manoj Gandhi, senior vice president and general manager of the Synopsys verification technology group, said Co-Design's technology will be used to improve Synopsys' HDL simulation tools, while SystemC will remain Synopsys' choice for system-level design. "This acquisition is strategically very important for Synopsys in accelerating our current Smart Verification strategy," said Gandhi. "We are trying to bring many high-level verification technologies into Verilog as part of VCS 7.0 [Synopsys' Verilog simulator].
"Co-Design has strong technology and technologists. Bringing them on board will accelerate our verification road map and accelerate the adoption of SystemVerilog," he added.
Gandhi said that Synopsys plans to advance both languages. Over the course of their development SystemC and Superlog have taken diverging paths, Gandhi said, with SystemC seeing greater use for hardware/software co-design and verification and with Superlog becoming valued as an extension to Verilog.
"SystemVerilog will evolve as the future for HDL," Gandhi said, adding that his company will continue Co-Design's work with Accellera in the standards group's effort to weave Superlog constructs into SystemVerilog.
Co-Design's Davidmann also downplayed the competition between the two languages last week. "People have thought that we competed with SystemC, but our focus has always been to evolve the HDL people to higher levels of abstraction," he said. "In a lot of ways the two languages are complementary. We've never seen them as that competitive.
"SystemC is getting huge attraction in the system-level design space, and Superlog or SystemVerilog is getting attention from HDL designers seeking an improvement on Verilog."
Accellera chairman Dennis Brophy said he does not see any ill effects coming out of the acquisition. On the contrary, he said, the move is likely to step up the rate of contributions from Synopsys, the creation of standards by Accellera and the adoption of those standards by users.
After the deal
Davidmann said he and his group of high-profile R&D engineers including Peter Flake, Co-Design's chief technology officer, and Phil Moorby, its chief scientific officer and the inventor of the original Verilog language plan to stay at Synopsys for a long time. Synopsys has said it will retain all of Co-Design's 18 employees.
Davidmann declined to state whether Co-Design was profitable or whether it was struggling in the rough economy.
"Our vision and our role was to extend Verilog into the future to make designers more productive," said Davidmann. "We brought a great team together and created a great product and had great success with all our early customers. What we could see was that Synopsys had the same vision and complementary technologies to evolve the language. The merger accelerates the vision we had."
But many system-level companies have not fared well in the down economy.
C Level Design, another system-level tool startup, closed its doors and sold all its assets to Synopsys at the end of 2001 when it failed to secure additional venture funding. In February, system-level company Cynergy System Design folded, and earlier this month, C-language design firm Celoxica laid off 10 percent of its work force.
Two of the companies that remain standing are Forte Design Systems and CoWare. Both said that their success has been in backing the right language and both were relieved that Synopsys placed Co-Design in its HDL simulator group.
"It's clear and encouraging that Synopsys understands that Superlog or SystemVerilog is an implementation language and that SystemC is a higher-level language focused more on hardware/software co-design," said Brett Cline, director of marketing at Forte. "Adoption of SystemC is growing, and we would have been nervous if Synopsys put Co-Design in its system-level group."
CoWare president and CEO and Alan Naumann said he knows "firsthand that more than 80 percent of the leading electronics and semiconductor companies have implemented or plan to implement SystemC into their design flow within the next 12 months. That, coupled with strong support throughout the EDA industry, makes it one of the big stories of the next few years."