SAN MATEO, Calif. As system implementations move to higher levels of integration, conventional semiconductor companies are finding that the real value of their standard-product portfolio lies not in chip sales but in the ability to license their designs as reusable intellectual property.
Infineon Technologies, for example, has long occupied a top spot in 16-bit microcontrollers with its C166 family. As standard products, these MCUs have established themselves in a variety of embedded-processing applications, based on high overall throughput, strong computational performance and system-level flexibility. With many of Infineon's key customers moving to higher levels of integration, the German giant was in a position to offer customers the compactness, low power and performance of the C166 in a code-compatible core by turning the design into synthesizable IP.
But migrating an older standard product to a synthesizable, technology-independent form for use in a system-level IC design is, to say the least, nontrivial. In the case of the C166, the original design was created via schematic capture in 1988. It had been moved to a cell-based form by 1995, but was not synthesizable. And certain architectural decisions had become increasingly archaic with the enormous changes in processes and performance levels in over a decade.
The solution for Infineon came in the form of a partnership. Synopsys Inc., busy building its IP library, was interested in the C166 as a synthesizable core and was willing to work with the Infineon designers to get it there. So the two companies worked together on moving the core from a cell-based hard macro to a synthesizable design.
Clearly, this would not be a simple process of unwinding net-lists and writing VHDL to describe them. Not only did the format of the C166 design have to be changed, but fundamental parts of the design needed altering too.
Perhaps more important, a nonproprietary verification environment had to be built that would be useful to licensees with no access to Infineon or Synopsys internal data.
The companies launched a formal planning phase just to understand the scope of the job. This led to a phased sequence of projects in which the existing hard macro was deconstructed, the verification suite was codified and a new RTL description, verification environment and script library were created.
Along the way, the core came in for some architectural fixes and more-detailed changes necessary for successful synthesis. Options were added to permit licensees to tune the core and its peripheral environment. Verification tools were added. In the end, the project took on the look of a new design in which the original specification had been in the form of a hard macro.
Synthesized versions of the core exceeded project goals in area, speed and power efficiency. As a study in rendering a macro synthesizable, the C166S synthesizable core demonstrates the true scope of such an undertaking and alerts designers to both the hidden opportunities and hidden engineering traps in a design conversion of this scale.
A case study on the C166 transformation, authored by Bertrand Noel-Baron of Infineon Technologies and Benedikt Schmaenk, Stefan Schmechtig and Robert Huber of Synopsys, is online at www.eet.com/story/OEG20020828S0031.