AUSTIN, Texas Intel Corp.'s announcement last week that it is adding strained silicon to its 90-nm technology mix stunned analysts and sent competitors into catch-up mode.
One analyst, Dan Hutcheson of VLSI Research Corp., predicted that Intel's surprise move to implement a form of strained silicon at the 90-nm node slated to move into manufacturing next year exclusively on 300-mm wafers at three Intel fabs will reverberate as widely as IBM's 1997 decision to implement copper interconnects at 180-nm design rules.
Senior technology managers at half a dozen companies said last week that they either have decided to add strained silicon to their technology mix or already have dedicated research teams working on the problem. "I think almost everyone in the industry is now on board with strained silicon," said Joe Mogab, a Motorola technology-planning manager and director of the company's Advanced Pro-cess Research and Development Lab (Austin).
Meanwhile, Intel's decision may boost the prospects of MIT spin-off AmberWave Technology (Nashua, N.H.). The 40-person company has developed a form of strained silicon that it has licensed to Advanced Micro Devices and to new AMD technology and foundry partner UMC Corp., among others.
Until last week, Intel had remained quiet about strained silicon, breathing not a word of interest at the various academic conferences, where the technology has become a mainstream research topic. As recently as June, at the 2002 Symposium on VLSI Technology in Honolulu, Intel managers adopted a skeptical pose, questioning whether strained silicon as IBM and others had described it would be worth the additional costs (see June 17, page 1).
But behind that curtain of public disdain, Intel was moving strained silicon technology into test manufacturing. In March it announced that test SRAM chips were being made at 90-nm design rules at its development fab in Hillsboro, Ore. What it failed to mention was that strained silicon was part of the process flow.
Even now, Intel has kept most of the details of its implementation to itself.
Mark Bohr, director of process integration and architecture at Intel's development facility in Hillsboro, said Intel has developed a form of strained silicon that enhances drive current by 10 to 20 percent but that adds only 2 percent to the cost of a processed wafer. Intel will be the first company to move strained silicon into manufacturing, Bohr said.
"We have figured out a way of changing the silicon lattice structure to allow faster electron flow a 1 percent change in silicon spacing to achieve a 10 to 20 percent increase in drive current. Intel is unique in that we can do this with no deterioration in terms of the short-channel effect or junction leakage," the Intel fellow said.
Intel will provide more but not much more information about its 90-nm process in San Francisco in December during a presentation at the International Electron Devices Meeting (IEDM), Bohr said. A more complete disclosure will come when products based on the strained-silicon approach ship next year.
One source said he had read the IEDM paper. He said the presentation indicates that Intel uses the conventional, graded silicon germanium approach but provides little information beyond that.
Intel will use the new process to make the Prescott Pentium 4 microprocessor. Production is slated to start next year in Hillsboro, then move out to a 300-mm fab being equipped in Ireland and then extend to Intel fabs in New Mexico and Arizona.
Head-to-head with Hammer
Intel's move at the 90-nm node sets up a head-to-head competition in the X86 processor arena between the Intel strained-silicon technique and the silicon-on-insulator approach taken by Advanced Micro Devices for the company's Hammer line.
In a thinly veiled reference to AMD, Sunlin Chou, senior vice president and general manager of Intel's technology and manufacturing group, said that "while some are slowly transitioning production to a 130-nm [0.13-micron] process on 200-mm wafers, we are moving ahead with the most advanced 90-nm technology exclusively on 300-mm wafers."
But AMD has its own ambitious technology road map. Craig Sander, vice president of technology development, said AMD's Fab 30 in Dresden, Germany, will be fully converted to 130-nm design rules soon and added that "it is looking very good for our 90-nm technology. AMD took a gamble on SOI [at 90-nm design rules], and that's our answer [to strained silicon]."
SOI-based SRAMs using the 90-nm process are in test production, and "demonstration vehicles" of AMD's K8 generation processor will be discussed soon, Sander said. Initial manufacturing of Hammer processors begins next year, with plans calling for Dresden to be converted to 90 nm by the third quarter.
Asked whether AMD might implement strained silicon at the 65-nm node, expected to move into initial production in two or three years, Sander said, "At this point I can just say that we have been working on strained silicon for some time with AmberWave, and we may mesh that work together with our technology development partner, UMC." AMD and UMC are building a joint-venture 300-mm fab, called the Au Fab, in Singapore for manufacturing at 65-nm design rules.
Sander said combining SOI with strained silicon presents "significantly greater" challenges than doing either approach alone.
UMC chief technology officer Frank Chen, speaking at a UMC technology day in Silicon Valley recently, announced that the foundry is working with AmberWave on strained silicon.
Taiwan Semiconductor Manufacturing Co. chief technology officer Chen-min Hu also has talked about TSMC's interest in the approach.
Sander further disclosed that AMD is readying a second-generation 130-nm process that will be used to manufacture AMD's Barton K7 processor, with a larger cache, in the second half of this year. That process will add a carbon-doped-oxide (CDO) as the low-k dielectric and will move to nine layers of copper interconnect (from seven in the current 130-nm process).
To date, IBM Corp. has been the main proponent of strained silicon, with a plan to add its version of strained silicon to IBM's 65-nm process node, expected to move to pilot manufacturing at the end of 2003 and into volume production in early 2005 on 300-mm wafers. IBM plans to combine its strained-silicon (SS) expertise with its silicon-on-insulator capabilities, for an SS-SOI process.
Bijan Davari, vice president of technology at IBM's Microelectronics Division, said Intel has not given the technology community enough information to judge whether its form of strained silicon is comparable to IBM's approach.
"The unanswered question is: What does Intel really mean by strained silicon? To us, it means a fairly high concentration of germanium, at least 20 percent or more at the top of the graded layer," Davari said. "If Intel is doing a lower level than that, it is almost a relaxed layer, and that will give you a 5 or 10 percent enhancement of current, which is relatively small. When you take the germanium content up to 20 to 30 percent, that is where it gets really interesting, with enhancements that are equal to one process generation, or about 30 percent.
"If they are saying their cost adder is only 2 percent, then they probably are not doing a whole lot. We estimate the initial cost adder will be about 10 percent, and that will go down as learning comes in and defect densities are reduced."
Hutcheson, president of VLSI Research (San Jose, Calif.), was more positive. "It is pretty clear that Intel has made a major breakthrough here," he said. "It is amazing that they would use strained silicon at the 90-nm node, and if the cost adder is only 2 percent, then the process additions would need to be pretty trivial."
A processed 300-mm wafer might cost $5,000 at the finished manufacturing stage, and a 2 percent increase in processing costs mainly adding a line of germanium deposition to a CVD cluster tool would amount to only $100 or so, Hutcheson noted.
Bohr said the addition of strained silicon, and a gate oxide only 1.2 nm thick, will support the faster circuits. The 90-nm NMOS transistors have a drive current of 1.2 milliamps/micron; the PMOS devices are rated at 0.6 mA/micron. That's a significant increase over the 130-nm process.
Intel also scaled the maximum operating voltage down to 1.2 volts, from 1.4 V in the 130-nm process. Bohr said scaling the operating voltage has become more difficult with each process generation, largely because there are limits to how much the threshold voltage can be reduced. Reducing the operating voltage is key to keeping power consumption under control, and Intel is likely to operate its mobile processors and other power-sensitive products at around 1 V at the 90-nm node.
Intel also has reduced the gate length, to about 50 nm, and will use 193-nm lithography for the four or five critical layers that include gate formation. Other than those critical layers, Bohr said, Intel will stick with 248-nm lithography for its 90-nm process.
Intel also will move to a carbon-doped oxide for the intermetal-level dielectric. The car-bon-doped oxide low-k material will provide an 18 percent reduction in the overall k value of the dielectric stack, which includes the insulator and etch stop barrier. For its 130-nm process, Intel used a form of fluorinated silicate glass (FSG) with a k value of 3.6. The CDO film used at 90 nm will take the k value down to around 3. Intel will add only one interconnect layer, moving to seven at 90 nm, to keep costs down, Bohr said.
While the company's use of a low-k dielectric and thinner gate oxide is business as usual, analysts said, the adoption of strained silicon came from out of the blue. "If they can do strained silicon with only a 2 percent cost adder, it's a slam dunk for Intel. Perhaps Intel has found a process edge that IBM hasn't thought of," said Rick Doherty, founder of technology analysis firm Envisioneering (Seaford, N.Y.).
Mark Wolf, chief executive officer of MIT spin-off AmberWave, said his intellectual-property-licensing company is working with customers, including foundries, who will bring products to market next year, using strained silicon at 130-nm design rules. Microprocessors, FPGAs and other performance-hungry chips will use strained silicon fairly soon, and beyond that mobile products will come to market that reduce the power consumption on a strained-silicon process,
he said. (By running a faster process on a lower voltage, overall power consumption will be able to be kept in check.)
Intel, Wolf said, "is better than anybody out there at bringing in a new technology to high volumes. Intel's announcement at 90 nm is way faster than anybody else in the industry, but we believe a number of companies that AmberWave is working with will have products ready next year at 130-nm design rules."