Platform-based design was introduced several years ago as a concept that would revolutionize chip design and redefine the future of systems-on-chip (SoC). But things haven't worked out that way. Some platforms are coming into use but reality has set in: Designing an initial platform isn't easy and using a platform involves trade-offs. Worse, there isn't a consistent definition of a "platform."
The basic idea behind the platform-based design approach is to avoid designing a chip from scratch. Some portion of the chip's architecture is predefined for a specific type of application. Usually there is a processor, a real-time operating system (RTOS), peripheral intellectual property (IP) blocks, some memory and a bus structure. Depending on the platform type, users might customize by adding hardware IP, programming FPGA logic or writing embedded software.
The good news is that a platform limits choices, thereby providing faster time-to-market through extensive design reuse. The bad news is that a platform limits choices by reducing flexibility and performance compared with a traditional ASIC or full-custom design methodology.
Still, most major semiconductor and systems providers are starting to employ platform-based strategies of one sort or another. "In some domains, such as wireless handsets or baseband processing, you would be hard-pressed to find a chip not designed with some level of platform in mind," said Grant Martin, Cadence Design Systems fellow and co-author of a 1999 book on platform-based design.
Platform-based design is really nothing new. Alberto Sangiovanni-Vincentelli, professor of electrical engineering and computer science at the University of California at Berkeley, noted in a March 2002 EEdesign.com feature article that PC makers have had a "platform" for years. It includes an x86 instruction-set architecture, a fully specified set of buses and a specified set of I/O devices.
Gary Smith, chief EDA analyst at Gartner Dataquest, takes the idea back even further three quarters of a century, to the days when reference designs came with vacuum tubes.
What is new, and somewhat controversial, is the platform concept applied to complex chip design, where much or all of a system is on a single chip. In this context, a platform essentially becomes an incomplete chip or system design there's an architecture, a processor and some preselected elements, but the designer must fill in the rest.
But defining what a platform is, and what platform-based design means, has been a can of worms. There are about as many definitions as there are platforms, making it hard to know what people are actually talking about.
Sangiovanni-Vincentelli, a key originator of the concept, defines a platform as a "layer of abstraction with two views." The upper view allows an application to be developed without referring to the lower levels of abstraction. The lower view is a set of rules that classify a set of components belonging to the platform.
Martin says platform-based design is "the definition and use of an architectural family, developed for particular types of application domains, that follows constraints that are imposed to allow very high levels of reuse for hardware and software components." As such, he said, it "moves reuse beyond the individual IP block level to reuse of architectures of hardware and software blocks."
"We define platform-based design as the creation of a stable microprocessor-based architecture that can be rapidly extended, customized for a range of applications and delivered to customers for quick deployment," said Jean-Marc Chateau, director of design for consumer and micro groups at ST Microelectronics.
The Virtual Socket Interface Alliance's (VSIA) platform-based design development working group (PBD DWG) hopes to have the final word by coming up with a taxonomy everyone can accept. That group defines an SoC platform as "a library of virtual components and an architectural framework, consisting of a set of integrated and prequalified software and hardware virtual components (VCs), models, EDA and software tools, libraries and methodology, to support rapid product development through architectural exploration, integration and verification."
Platform-based design, the group says, is "an integration-oriented design approach emphasizing systematic reuse, for developing complex products based upon platforms and compatible hardware and software VCs, intended to reduce development risks, costs and time-to-market."
All these definitions leave a lot of questions on the table. Is an application-specific programmable product (ASSP), differentiated only through embedded software, a platform? If there's a predefined interconnect architecture but no processor, is it a platform? Is an FPGA-based ASIC development board a platform? Are derivative design and platform-based design really the same thing?
Advantages and challenges
The most frequently-cited advantage of platform-based design is time-to-market savings. Once you've got an architecture and some predefined blocks, knocking off derivative chips should be fast and easy, at least in theory. Bob Altizer, president of Basys Consulting and chair of the VSIA's PBD DWG, sees other advantages as well. One is verification reuse, and another is an ability to work at a systems level and do chip integration at a high level of abstraction.
"Design is getting really tough, so you want to do fewer designs, and you want those designs to apply to a broad variety of applications," said Kurt Keutzer, professor of electrical engineering and computer science at U.C. Berkeley. Keutzer, who heads up a Gigascale Silicon Research Center (GSRC) "thread" on programmable platform-based design, is a strong advocate of that concept (see "High on Mescal," page 96).
Time-to-market savings was a strong motivation for the Philips Semiconductor design team that created both the Nexperia Digital Video Platform (DVP) and the first iteration of that architecture, the pnx8500 media-processing chip. Augusto de Oliveira, chief architect of digital consumer systems at Philips, said he thinks future chips based on the DVP will let his company reduce both design times and team sizes by 50 percent; he feels this starting to happen with current projects.
But that's not the first chip out the door. Designing the initial platform, along with the pnx8500, wasn't quick and easy. It involved about 300 hardware, software and systems people working between 1999 and 2001, of which 60 were involved with hardware.
And that's the rub. "Designing the platform requires fairly large design teams, and it's a pretty big bet for the company that's doing it," said Cadence's Martin.
VSIA's Altizer puts it bluntly. "If today's grand platform is not suitable for design a year from now, you will have gone down an elegant but extremely expensive dead end," he said.
Platforms must change and grow over time, Oliveira said. "Our model is to leap forward with the platform about every two years, and during the intermediate time, have quite a bit of derivative creation." In its upcoming second generation, for example, Nexperia DVP will shed its tristate PI bus and replace it with an asynchronous bus that connects what Oliveira called "islands of synchronicity."
Some critics believe that platform-based design is ultimately too inflexible to be broadly applicable. "It works well for a small niche, but it can't work for most designs," said John Cooley, moderator of the E-Mail Synopsys User's Group. "You've got to have a fully defined problem, and most designs are on the fly."
Dataquest's Gary Smith says platforms won't work for most SoC designs, because if an architecture is frozen, the ability to use silicon as a competitive advantage is severely limited. Where it will work, he says, is in embedded design, where the differentiation is in software rather than hardware (see "Comment," page 95).
Keutzer said that Smith's notion of "SoC design," in which the competitive advantage is in custom silicon, will not be a viable approach to design in the future. "You cannot simply take an ad hoc methodology, go through IP repositories, hook pieces together and come up with reliable ICs," he said. "The IP assembly era of chip design just never showed up."
Altizer believes platform-based design will become a "major paradigm," provided it can make an important shift. "Most of the activity to date has been a bottoms-up approach, where you put together designs to serve specific domains and try to reuse them," he said. "I see a transition going on to a greater concern with systems and software issues, and full system-level support."
Types of platforms
One way to get a handle on platform-based design is to categorize the types of platforms available today. In a paper given at this spring's Electronic Design Processes (EDP-2002) workshop, three Cadence authors identified four types of platforms.
First of these is a "full-application platform," in which users design full applications on top of hardware and software architectures. In general, there will be a processor, a bus and application-specific blocks, such as modems or MPEG decoders. Examples include Nexperia, Texas Instrument's OMAP multimedia platform, Infineon's M-Gold 3G wireless platform, Parthus' Bluetooth platforms and ARM's PrimeXsys wireless platform.
The second type is a "processor-centric platform," which focus on access to a configurable processor but doesn't model complete applications. Examples here might include Improv Systems, ARC, Tensilica, and Triscend.
The third type is a "communication- centric platform," which defines an interconnect architecture but doesn't typically provide a processor or a full application. Examples include Sonics' SiliconBackplane and PalmChip's CoreFrame architectures.
The fourth type is a "fully programmable platform," typically consisting of FPGA logic and a processor core. Examples include Altera's Excalibur, Xilinx' Virtex-II Pro and Quicklogic's QuickMIPS. The recently announced Xilinx-IBM XBlue architecture, which brings FPGA logic into an ASIC architecture, may fit here or be a related category.
"People have started bandying around words, so our motivation is to put a stake in the ground and say, 'here's what we see as four categories,' " said paper co-author Stan Krolikoski, vice president of business operations at Cadence's systems and functional verification group. "We're not claiming to have everything nailed down, we're just trying to start a discussion."
Altizer commented that these four categories present "a pretty good initial statement of things," but he noted that one type of platform may include another. For example, a full applications platform might also have a configurable processor.
GSRC researcher Robert Passerone has presented a different map of the platform world. At the top are "service platforms," in which higher-level services are implemented on top of a network, as with Ericsson's Internet Services Platform. Next are "application platforms," upon which users develop raw applications, such as Intel's Personal Internet Client Architecture (PCA). Then come "system" platforms such as Nexperia, OMAP and PrimeXsys.
Potentially adding more confusion to the mix is the notion of "ASIC development platforms," as offered by LSI Logic and other ASIC providers. These might include a combination of FPGA logic and application-specific cores with a bus architecture. But it's for prototyping and software development only the final logic is implemented not in the FPGA, but in an ASIC.
Philips' Nexperia is one of the best-known examples of a full SoC applications platform. Nexperia DVP includes a 32-bit MIPS RISC CPU, a Philips 32-bit VLIW TriMedia processor and three levels of internal buses. Users differentiate their chips through a library of software, as well as hardware, IP blocks. A prototyping tool, the Nexperia Advanced Prototyping Architecture (NAPA), lets users simulate the functioning of selected IP blocks before committing to production.
Nexperia is designed for use both within and outside Philips and serves both ASSP and ASIC design strategies, Oliveira said. He affirmed that Philips is working with "all major consumer electronics vendors" but has not yet made public announcements about external Nexperia licensees. In addition to Nexperia DVP, there are Nexperia platforms for mobile battery-power devices and for car "infotainment" systems.
ARM's PrimeXsys is an extension of ARM's CPU licensing model to include peripherals, a choice of operating systems, and software and hardware development tools. The first available platform is the PrimeXsys Wireless Platform. It includes the ARM926EJ-S processor core, Java acceleration, a multilayer AMBA bus and a selection of peripherals. Licensees include ST Microelectronics, Sanyo and Philips.
A PrimeXsys Dual Core platform, set for fourth-quarter release, will target applications like cable modems, xDSL modems, WLAN access points and SoHo routers and switchers. But ARM does not intend to stop there. "The philosophy is that it [PrimeXsys] is designed to be extended," said John Goodacre, ARM's PrimeXsys program manager.
Indeed, ARM joined forces with Philips and with DSP provider Adelante Technologies last June to develop a common, open SoC development platform for mobile entertainment applications. The companies plan to finish a "proof of concept" by the end of this year.
First introduced in 1999 for 2.5 and 3G cell phones, TI's Open Media Applications Processor (Omap) is among the most venerable of all platforms. Until last month, however, it was aimed at major wireless vertical companies such as Sony, Nokia, Ericcson and Sendo, some of which are now shipping products based on Omap. The August rollout of the TI OMAP5910 represents the first rollout to the "broad market," said Greg Mar, worldwide manager for marketing and business development at TI's DSP group.
The OMAP5910 includes TI's TMS320C5xx DSP, a TI-enhanced ARM processor, and an interprocessor communications mechanism. With a choice of operating systems, it's aimed at applications that include wireless handsets, PDAs, telematics, gaming consoles and others. But it's not just an architecture, it's a pre-manufactured chip. If designers want to add their own hardware IP blocks, it will have to be off-chip.
The value of this approach, said Mar, is extremely high integration and fast development times. "We've taken care of all the lower-level architecture and integration," he said. "Both hardware and software developers can get up and running in a matter of hours with an Omap platform, and add their own value."
A configurable approach
Improv Systems' Programmable System Architecture (PSA) platform is of a very different nature from Nexperia or Omap. PSA lets users interconnect multiple Jazz DSP processors, which are individually configured for a given application. There's a structure called the Q-bus that acts as a unified task management and control bus, but doesn't transmit data to the processors. Users can add ARM or MIPS cores, but they aren't provided.
Cary Ussery, Improv president and CEO, said his company wants to be different. He said that an architecture such as Omap is a "fixed platform" with pre-determined hardware resources, in contrast to Jazz, which is a configurable processor. "The whole platform should be that way," Ussery said. "You should be able to take the platform, select the right resources and create something optimized for your applications domain."
Improv customers include Philips and Kawasaki. Improv provides a complete suite of hardware and software development tools, and in July, the company introduced its application-specific Crescendo solution kits, starting with broadcast media and mobile media.
Sonics is another company that isn't offering a full applications platform. In fact, the company is really a provider of IP that happens to offer an interconnect architecture. Sonic's SiliconBackplane MicroNetwork provides an on-chip "network" that lets users attach, and decouple, multiple IP blocks.
Where platform-based design needs to go, said Drew Wingard, Sonics CTO, is toward support of SoCs with multiple "tiles." A tile is a fairly independent subsystem that has local memory, I/O resources and, most likely, a control processor. Wingard said that future SoCs will encompass a number of such tiles, and he said one customer, who he declined to name, just completed a "triple tile" design with a half-dozen DSPs.
What's needed is an interconnect architecture that can abstract away the details of the tiles, and that's what Sonics plans to provide. Wingard said the SiliconBackplane MicroNetwork can handle both communications within and between tiles, whereas the widely used Amba bus, he claimed, is suitable only for communications within a tile. In the future, he said, Sonics will offer specific products aimed at communications within and between tiles.
The maximum flexibility comes with fully programmable platforms, but the trade-off is price. Current offerings from FPGA vendors come with per-unit costs ranging from tens to hundreds of dollars. "The $64,000 question," said Cadence's Martin, "is whether [FPGA platforms] can break out of the high-end infrastructure equipment market and into a more consumer-oriented approach. You need the right combination of performance, cost, time-to-market and flexibility."
Keutzer sees another challenge the lack of a single, integrated "programmer's model" for these devices, which is the goal of his GSRC research work. "Today you've got to program the ARM processor in the ARM environment, then develop the FPGA with Verilog, and then do co-simulation this is not an integrated programming environment," he said.
It may be a little early for that. Hybrid devices that contain embedded processor cores and FPGA logic are relatively new innovations. Xilinx in March announced the Virtex-II Pro, which contains an embedded 300 MHz PowerPC processor, serial I/O transceivers, and an FPGA fabric, all linked with IBM's CoreConnect on-chip bus. It comes with Wind River Systems' VxWorks operating system and software development tools. Prices range from less than $20 to $1,500 per chip.
Xilinx calls both the Virtex-II Pro, and its Virtex-II predecessor, "FPGA platforms," even though the The Virtex-II contains a soft processor only. Steve Sharp, senior marketing manager at Xilinx' product solutions group, said it's too early to name customers for the Virtex-II Pro, but he said the Virtex-II has been adopted by Alcatel, Allegro Networks, Pinnacle Systems, Mercury Computers, PMC-Sierra, Agilent, Bivio Networks and others.
Sharp could not say how many Xilinx customers today are using platforms, but he's optimistic about the future. "I think three years out, it's fair to say, a majority of our customers will be designing with [platforms]," he said.
Altera has been shipping its Excalibur "systems on programmable chip" since last fall. Excalibur includes an embedded ARM922T RISC processor and an Amba bus, and also permits use of Altera's configurable Nios processor. Alcatel is one announced customer. Altera parts using Nios sell for as little as $20, and the ARM core adds only "tens of dollars," said Tim Southgate, Altera's vice president of software tools and marketing.
Altera provides a range of operating systems and software development tools. "One thing we're having to do as a hardware company is come to grips with the software guy," Southgate said. "We're delivering tools to software engineers, and we're finding that the lines between hardware and software are getting fuzzy."
Quicklogic has been shipping its QuickMIPS platform since the beginning of 2002. It contains a 175-MHz MIPS4Kc processor, a PCI interface, a memory interface, a 110 Base T Ethernet MAC, an Amba bus, and up to 500,000 system gates of programmable logic. John Birkner, Quicklogic CTO, declined to name customers but said that "a number of designs are going on." Costs are in the "under $100" range, he said.
Quicklogic was a pioneer of the FPGA-plus-hard-core concept, having offered its embedded standard product (ESP) devices for several years now. These started out with PCI cores. The QuickMIPS is the first member of the ESP family with a hard processor core. "ESP is our fastest growing segment, and we expect QuickMIPS to be a major portion of that," Birkner said.
What's needed to bring platform-based design into the mainstream, and to provide new generations of platforms, is a methodology and design flow. "Platform-based design does not have a well-understood design flow, as RTL design does," said VSIA's Altizer.
The methodology must address both the creation of platforms and the use of platforms to produce quick derivative products. Also needed is a well-defined handoff between platform creators and consumers, and that's exactly what the VSIA's PBD DWG hopes to outline.
Need for standards
"First off, we need standards," said Cadence's Krolikoski. "We have no uniform way of talking about platforms. Then we need tools at multiple levels for architects, designers and users of platforms. The question is, where's the pivot point where's the level above RTL that all three categories can use."
Martin thinks new technology is needed. "We need to describe the function and then automate the creation of implementations that function in a hardware, software or combined form," he said. "It may be time to look at high-level synthesis approaches of a different kind. The old generation only drove hardware architectures." Martin said he believes a "language infrastructure" is starting to emerge with SystemC that will drive the creation of new analysis tools for platform creators.
For platform consumers, the question is the development of a unified programmer's model. Keutzer sees two possibilities. One involves a real-time embedded software approach and looks much like today's software development methodology, in which there's little awareness of the silicon target. Another stays close to the silicon, using tools such as Matlab or Xilinx' DSP compiler.
"I personally feel that our fundamental limitation in developing programming models is our lack of insight into concurrent applications," Keutzer said. "We just don't understand the right way to build large concurrent systems. There's fairly fundamental work to be done there."