AUSTIN, Texas Ziptronix Inc., a spin-out from the Research Triangle Institute, said it has created a unique wafer bonding technique that enables three-dimensional chips.
The approach can join logic devices with memory, or logic with analog components, the company said. It could also be used to mount RF filters onto other RF components, or bond silicon or silicon germanium devices with chips made in III-V materials, the company said.
J. Douglas Milner, chief executive officer of Ziptronix (Research Triangle Park, N.C.), said his company's bonded approach will allow a combination of different circuitry logic fabricated in a logic process; analog produced in a higher-voltage process; and DRAM built in a memory process to be joined by die-to-die interconnects while sitting only a few microns apart, leading to extremely short propagation delays.
Research into wafer bonding started at the Research Triangle Institute in the early 1990s, led by bonding expert Qin-ye Tang and eight others. That work became the cornerstone of Ziptronix when it was spun out in September 2000.
The method remains proprietary, but a key point is that the bonding happens at room temperature, and does not require pressure or thermal activation that could affect active circuitry.
The creation of a 3-D chip for Ziptronix starts with a target wafer and another wafer that holds so-called donor memory chips. Both are treated with a proprietary chemical process that readies the wafer surface for bonding. The donor chips are singulated, and a pick and place machine aligns the interconnect pads of the two devices the logic device on the target wafer and the treated, unpackaged donor die and puts them together, creating a tight bond, said Robert Markunas, a Ziptronix co-founder and its vice president of market development.
"The strength of the bond is about the same as the fracture strength of silicon," said Milner.
The layers of Ziptronix's 3-D circuit include a metal interconnect (at top), followed by a memory substrate, several memory layers, a bond interface,then logic metal, logic transistors and a logic substrate.|
After a bond is created at the active, circuit sides of the two die, the backside or substrate sides of each die are thinned, first with grinding and then with a chemical mechanical polishing step. Next, a five-mask-layer interconnect step is used to etch vias and connect the two die, and to create the connections to the circuit board, either as bumps or as wire bond connections.
Markunas said the etching process is below the pad ring and does not affect active circuitry. "With our approach, the interconnects between the two die are less than 10 microns apart, in some cases as little as 3 microns in distance, which is comparable to the length of on-chip interconnects on an SoC. That allows us to do interconnects at on-chip speed. If a microprocessor operates at 2.8 GHz, we don't have to rely on the front-side bus of perhaps 133 MHz to connect to memory, we can connect at chip-level speeds."
Markunas said the cost of integrating a target wafer with donor chips is in the range of $500 per wafer, including the interconnect steps. That is at least a 50 percent savings over a system-on-chip or 2-D design, and the time-to-market can be halved as well, Milner said.