SAN JOSE, Calif. Embedded systems designers are cozying up to the idea of implanting 64-bit processor engines into their system-on-chip (SoC) designs, at least in small doses. One company taking small steps in that direction, Tensilica Inc., plans to tell the Microprocessor Forum here this week that an upcoming architecture will let users define their own 64-bit instructions for greater parallelism without tossing out the original 32-bit core Xtensa architecture.
Tensilica's Flexible Length Instructions Extensions (Flix) were created as an alternative to more-common approaches to boosting processor performance. One idea considered and rejected was superscalar, which the company said is too heavy-handed for an embedded core that needs to be small and power-efficient. "The cost of all the predictive logic required to do that [means] there's little payback in the SoC world," said Steve Roddy, director of product marketing at Tensilica (Santa Clara, Calif.).
The company then looked at very long instruction word machines, in which one instruction is broken down into smaller pieces and executed in parallel. But typically every word has to be 64-bits wide or larger, swelling the size of the processor, the ROM and the cache to the point that it becomes hard to put multiple cores on a chip, Roddy said.
Gain in parallelism
In the end, Tensilica decided to retrofit the original RISC architecture to take in customized 64-bit instructions as a way to get more parallelism, not as a generic addressing scheme. The most likely target for these instructions are inner loops, those core algorithms that can hammer away at the processor for tens of millions of cycles without pause. With the company's existing Xtensa architecture, these inner loops are handled by putting together 16- and 24-bit instructions in many variations, a scheme that can be inefficient.
"Today you might want to do several things in one instruction an add, compare and lookup but you have to do one autonomous instruction for that add, compare and lookup," Roddy said. "If you have lots of permutations of those from different register sets . . . you have to create a large number of compound instructions."
With the Flix architecture, by contrast, "you can create a larger op code word, and each of those becomes autonomous, to more quickly create compound instructions without limiting the flexibility," he added.
To be sure, 16- and 24-bit instructions still make up the core of the instruction-set architecture.
In most cases Tensilica expects designers will use 64-bit instructions sparingly, perhaps for specific algorithms with a crying need for parallelism. More-generalized 64-bit computing, however, is still overkill for most applications, the company said.
"You don't see a lot of regularized 64-bit data in most applications," Roddy said. "Here the flexible instruction length is part of the [custom] instructions as opposed to the base machine. The basic ISA is still 16 and 24 bit."
Some Tensilica customers are already preparing to deploy their own implementations of Flix.
Conexant Systems Inc. (Newport Beach, Calif.), which owns a stake in Tensilica, helped develop the Flix architecture and this week is set to describe a DSP-like processor that uses hundreds of custom 64-bit instructions. The processor supplanted a proprietary DSP project Conexant was considering, according to Tensilica.
For others, the 64-bit instructions won't be needed at least not immediately. Xtensa in its current form is sufficient to build USB interface chips that can handle more bit manipulation, such as encryption and copyright protection functions, said Jeff Chang, product-marketing manager for the wired personal communications division at Cypress Semiconductor Corp. Cypress has just taken a license for Tensilica's processors and design environment.