Over time, sample rates in analog-to-digital converters have increased steadily, thanks to some of the same technology improvements that have increased the speed and density of digital ICs. Decreasing CMOS channel lengths and bipolar transistor base widths have resulted in devices that can operate at hundreds of megahertz and that provide sufficient gain for analog processing.
As silicon geometries shrink, they require lower power supplies, allowing for lower power dissipation while maintaining adequate breakdown voltage margin. IC power supplies have migrated from 5 volts for TTL, which was the workhorse in the 1970s, to 3 V to 1.8 V and lower for CMOS; logic swings have been reduced commensurately.
Inclusion of digital functional blocks on the same silicon as analog blocks in mixed-signal systems has resulted in high-frequency analog processing in noisy environments, requiring specialized architectures and techniques at the chip level. This is also true at the printed-circuit board level, where sensitive analog signals need to coexist with "noisy" digital signals.
High-speed A/D converters typically obtain some isolation from digital switching noise by maintaining separate power supplies on-chip: one for the analog and a second for the digital outputs. Standalone A/D converters typically interface to variable capacitive loads and to larger loads than integrated A/D converter cores. A/D converter cores typically drive a fixed internal load, with lower capacitance than that of the standalone device. Standalone A/D converters also have more complex power-busing constraints. Lead frame and wire bond inductance effects become more important as edge rates speed up to meet high-frequency operation demands. A/D converter cores can digitize today at encode rates of 200 MHz or more at 12-bit resolution. That's impressive, given that 20-MHz 12-bit A/D converters were considered state-of-the-art in 1992.
But providing rapid data outputs at these frequencies is a challenge. One solution is to multiplex the output data stream onto two separate output ports. That option reduces the output data rate by a factor of two; in other words, two 100-MHz buses provide an effective 200-MHz throughput. Obvious disadvantages are the increase in output pins required and the synchronization issues encountered in multiple A/D converter systems.
A better solution, which can offer very high-speed operation while minimizing complexity and maximizing performance, is the use of low-voltage differential signaling (LVDS). Basically, LVDS is a new differential logic family that requires two pins for each signal and is well-suited for high-speed digital transmission. It provides current outputs and requires a 100-ohm termination resistor at the receiver input (far end of the line). The nominal output current per driver is 3.5 mA, resulting in a 350-mV voltage swing at the receiver's input.
The LVDS output common-mode voltage specification is approximately 1.2 V and is maintained by a common-mode control circuit that is not shown. A 100-ohm differential termination resistor translates the current output to a voltage and provides transmission line impedance matching to the two 50-ohm signal traces, minimizing such transmission line effects as reflections and ringing.
LVDS has some additional advantages over CMOS for A/D converter data output transmission. Standard CMOS logic runs out of gas at 125 MHz or so. Higher-speed data-transmission applications must turn to ECL, PECL and now LVDS. The differential outputs have an inherent common-mode rejection advantage and can handle ground offsets between driver and receiver.
CMOS output buffers typically drive a load capacitance on the order of picofarads. The current required to charge and discharge this load in a nanosecond or so creates a voltage spike equal to L di/dt across the inductive power supply and ground pins on the A/D converter (ground bounce). This current surge is a source for electromagnetic coupling to the analog section of the A/D converter at the package level; the coupling results in ac performance degradation at higher analog input frequencies and/or sample rates.
LVDS, on the other hand, essentially steers a constant current through a termination resistor, so there is minimal transient load activity on the output supplies. This greatly reduces the potential for cross-coupling of the outputs to the sensitive analog front end.
Data sheets for highspeed A/D converters with CMOS outputs typically recommend that the A/D converter be placed close to the receiving logic to minimize the load capacitance and to avoid the deleterious effects of transient load currents. Unfortunately, this can place the A/D converter right next to a source of significant switching currents, radiation and heat generated by the receiving logic, ASIC or FPGA.
An A/D converter with LVDS outputs provides balanced current outputs. The A/D converter can therefore be placed several inches or more from receiving logic, thus obtaining some physical isolation from noisy circuits. A fast Fourier transform performed on the AD9430, a new 12-bit high-speed A/D converter with LVDS outputs, shows that data can be sampled and pulled out at 100-MHz rates. A sample clock of 210 Msamples/second, digitizing a 70-MHz analog input, produces a signal-to-noise ratio (SNR) of 63.7 dB.
LVDS signals tend to generate less electromagnetic interference than single-ended CMOS signals due to the differential outputs. Trace-length skew between differential outputs should therefore be kept to a minimum to maximize this benefit.
However, LVDS does have a disadvantage in power dissipation compared to CMOS. LVDS power dissipation is constant and does not scale linearly with clock rates as in CMOS; at low sample rates CMOS can dissipate less power than LVDS. As sample rates increase, CMOS power dissipation will increase linearly with sample rate, eventually requiring more power than LVDS. At sample rates equal to 200 Msamples/s, LVDS and CMOS power dissipation are comparable.
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