DALLAS Texas Instruments Inc. executives are claiming that their choice of ferroelectric RAM for embedded memory at the 90-nanometer node and beyond will give TI a competitive edge over companies adopting embedded flash, DRAM, MRAM and chalcogenic memories.
Speaking at the annual Gartner Dataquest semiconductor conference in Los Angeles this week, Hans Stork, senior vice president and director of TI's silicon technology development, said the company has built a 64-Mbit FRAM module using its 130-nm copper logic process. The FRAM module requires only two additional mask layers and has a cell size of 0.54 square micron, 2.5 times smaller than the 1.95-micron2 SRAM cells on the same chip.
By the time FRAM is deployed in the field, the Dallas-based chip maker will be using a 90-nm process that will shrink the FRAM cell size to 0.35 micron2, Stork said.
TI expects to deploy the FRAM technology within its 90-nm node, primarily for cell phone chip sets. Embedded FRAM also could be used within DSPs and in single-chip solutions developed for high-volume consumer and networking markets.
"We believe FRAM has the potential to become an ideal non-volatile memory option for a wide range of applications in the 2005 time frame," Stork said, adding that "TI believes FRAM can change the product dynamics in embedded memory."
At the International Electron Devices Meeting set for Dec. 8-11 in San Francisco, TI and its FRAM development partners, Agilent Technologies Inc. and Ramtron International Corp., will detail the material set and manufacturing steps required to build an FRAM module within a 130-nm logic process.
TI and Ramtron signed a multimillion-dollar FRAM licensing deal in August 2001 that started TI on the track toward commercializing the technology, which to date has been limited to relatively small densities.
TI has created a 64-Mbit FRAM module, using iridium electrodes and a thin lead-zirconate-titanate (PZT) ferroelectric layer, Stork said. Starting at the contact layer, TI sputters the iridium electrode, and then uses a molecular-oxide chemical-vapor deposition process for the thin-film PZT layers.
TI vice president Dennis Buss said that while the company has an embedded-flash capability that it deploys for automotive controllers, embedded flash "made no sense from a cost point of view for the cell phone market vis--vis the cost of stacked flash" that is, putting bare logic and flash dice in stacked packages.
Both embedded DRAM and embedded flash require an additional six to eight mask layers on top of the 26 or so masks needed for logic. Embedded DRAM also requires burn-in steps that can add about 70 cents per chip, Buss said.
The pseudostatic embedded memories, such as the Mosys Inc. 1T SRAM, can require four to eight additional mask layers, with relatively high power dissipation, he said.
"The real reason that we like FRAM is that it replaces embedded RAM but has zero standby power consumption. If you look at embedded SRAM, the static power can be quite high," said Buss.
'Not as mature'
Intel Corp. has endorsed Ovonic memory, a form of chalcogenic material, but Buss said Ovonic memory arrays will require four additional mask levels, "and Ovonic is not as mature a technology as FRAM." Similarly, Motorola Inc.'s magnetoresistive RAM, or MRAM, has yet to be proved cost-effective.
TI is developing chips with a combination of on-chip SRAM and on-board FRAM in order to deal with the challenges presented by the destructive read characteristic of FRAM. A read requires a change in the polarization state of the ferroelectric stack. After the read, the data must be written back, which increases the number of write cycles over the lifetime of the chip. TI rates FRAM's write endurance at 1014, one order of magnitude less than either SRAM or embedded DRAM.
"There was a significant amount of work that had to be done by TI and Ramtron to solve some of the unique challenges presented by FRAM materials," Buss said. "One of them was the write-erase endurance. We had to find ways to work around it by combining FRAM with small SRAM modules, and keeping some of the heavier write cycles in SRAM."