Scan is the most general and pervasive digital structural-test technique, one that has been a standard in the industry for years. However, scan-design methodologies have not improved in all that time. The traditional methodologies do not use resources for scan design efficiently, which results in suboptimal scan designs in terms of test time, test interface and test power.
Most important, the frequency of the scan I/O ports is completely ignored as a resource and is typically restricted to the frequency of the internal scan chains during test. Since the internal scan chains are typically designed to operate at a low frequency for reasons of test power and design effort, the scan frequency gets tied to a low value as well. This results in a bandwidth (pins x frequency) bottleneck across the scan interface, especially if the automated test equipment (ATE) is capable of providing higher bandwidth.
The traditional coupling between scan I/O frequency and internal scan frequency can be broken by using a technique called bandwidth matching. In this technique, the scan chain or chains and the scan I/Os are connected through one or more bandwidth-matching elements. That makes it possible to decouple the internal scan frequency from the scan I/O frequency-as long as the bandwidth requirements on either side are matched.
The bandwidth-matching elements allow designers to perform pin (space) vs. frequency trade-offs and enable flexible design of internal scan architectures (narrow or wide) within the bandwidth-matching constraint to achieve the goals in terms of test time, test interface and test power. These bandwidth-matching elements can be easily implemented using either a shift register or a demultiplexer/multiplexer pair.
The time it takes to do a scan test for a design can be reduced with bandwidth matching if there is extra bandwidth available at the I/O. The original scan chain can be split into multiple scan chains; this reduces the depth of the scan chain, which determines the test time for a given scan frequency. For example, the extra bandwidth available at I/O can be used to split the original scan chains into two to reduce the scan depth to 50 instead of 100. This cuts test time by 50 percent without increasing the number of scan I/O ports. In general, the test time reduction is linear to the bandwidth ratio of the I/O bandwidth and the internal scan bandwidth.
The extra bandwidth at the I/Os can also be used to reduce the number of scan ports required for a scan architecture. In this case, instead of using one scan-port pair to connect to one scan chain, multiple internal scan chains are connected to the same port using bandwidth matching, up to the maximum bandwidth available at that I/O. This reduces the overall scan port requirements.
When the approach is applied to reducing chip consumption and dissipation effects, use can be made of the fact that power is proportional to frequency. If we can drop the frequency, the total power will also drop.
However, for a scan chain, if the scan frequency is reduced, then test times are increased. But if the scan chain is split into multiple segments by a factor that is equal to the drop in the frequency, then the test time will remain the same because the scan depth drops by the same factor.
In addition to benefiting the device, the bandwidth-matching technique enables better ATE designs. The effect of decoupling the internal scan frequency from the I/O frequency, enabled by bandwidth matching, undermines the basic assumption upon which low-cost structural testers often have been proposed. Instead, this decoupling makes it possible to design cost/frequency-optimized ATE systems.
To take advantage of the proposed technique, one would need to design bandwidth-matching elements that can be easily implemented using shift registers. Moreover, if the insertion of these elements is supported by the design-for-test synthesis tools, then it can be made completely transparent to the user in terms of scan implementation. One can use higher pad frequencies to increase the bandwidth and get better benefits. Of course, higher-frequency pads will also need higher frequencies from ATE. But modern, well-integrated ATE can run up to hundreds of megahertz easily without adding any significant cost, especially when one considers that in scan tests, accuracy requirements are not high.
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