SAN MATEO, Calif. Chip makers are clamoring to show off technology that can transfer serialized data at speeds of 10 Gbits/second, but are customers ready to bite?
Xilinx Inc. thinks they are. To back up its belief, the company last week announced that it has fabricated a test transceiver chip that runs at 10 Gbits/s. Xilinx plans to ship FPGAs with transceivers running at such speeds later this year.
What makes the move noteworthy is not just that Xilinx has 10-Gbit/s serial technology in hand; several other chip makers can make the same claim. Rather, the company thinks the technology can serve more than a niche and that it is ready to be deployed in the form of off-the-shelf, programmable chips suitable for many applications.
"We're targeting a broad range of applications that includes a number of [board] materials and distances," said Chuck Tralka, marketing director for Xilinx's advanced products division.
But some chip companies holding the keys to transceiver technology are less confident that the market is ready to shift to faster speeds. Fujitsu Laboratories recently announced a 10-Gbit/s CMOS transceiver core that it plans to sample this year, but executives said they may turn down the speed.
"Currently we don't see a business market for 10 Gig," said Hirotaka Tamura, a researcher at Fujitsu Laboratories, adding that the company may consider a 5-Gbit/s solution.
Broadcom Corp., which came out with its first 10-Gbit/s chip three years ago for optical modules, thinks 10-Gbit transceivers are still a tough sell in most other areas.
For example, some companies are looking to adopt higher speeds of Xaui, running at 5 to 6 Gbits/s in backplanes, "but I haven't come across an application to date that requires running a backplane at 10 Gig," said Ali Ghiasi, chief scientist at Broadcom.
While faster serial transceivers can reduce pin counts, the cost of integrating multiple transceivers on an ASIC that operates at such high speeds may still be too high. "Today you can integrate 32 Xaui cores, but if you want 10 Gig and you can only use four of them, you're losing significant bandwidth out on that ASIC," Ghiasi said.
Xilinx, however, believes that even tough market conditions shouldn't slow the steady march to higher speeds, fewer pins and smaller device footprints.
"All these things are big advantages," Tralka said. "And by moving to high-speed serial the clock becomes embedded, which means clock skew issues associated with source-synchronous [interconnect] go away."
Even so, the company recognizes that customers are not going to buy into a technology unless they're convinced it will ultimately save them money. "Customers expect to increase bandwidth while simultaneously decreasing system cost. That presents a big challenge for those of us providing silicon to those systems," Tralka said.
From a cost standpoint, one favorable attribute of Xilinx's homegrown 10-Gbit/s transceiver technology is that it takes up about as much die area as the 3.125-Gbit/s transceiver that Xilinx licensed from Mindspeed Technologies and incorporated into current XIlinx FPGA products. Another is that it can be fabricated in standard CMOS.
Moreover, the Xilinx transceiver is based on conventional nonreturn-to-zero signaling techniques as opposed to multilevel signaling, which is "not interoperable with anything," said Tim Hemken, marketing director for the communications technology division.
Publicly, Xilinx is showing a captured image of an eye diagram of its transmit signal that has a height of 455 millivolts and a width of 86 picoseconds. That demonstrates "a significant percentage of the overall signal transition time available as a clean signal," Tralka said. Xilinx has not disclosed such other details as signal conditioning, board materials, signal length and signal quality at the receiver end.
Xilinx is just one of several companies that have joined the 10-Gbit/s club. At the International Solid-State Circuits Conference last month, researchers presented four papers describing transceiver circuits operating at 10 Gbits, an indication that companies are pushing the bounds of copper-link signaling despite the bleak market.
Fujitsu's transceiver, based on an 0.11-micron CMOS process, transmits signals at 10 Gbits/s over multiple channels using a single 1.2-volt power source. Fujitsu was able to get by with a relatively low-power source by employing quasi-digital circuits known as phase interpolators instead of more power-hungry phase-locked loops. The circuits convert a signal into phases and synthesize it with a reference clock without the use of an oscillator, thus lowering power consumption. The transmit channel consumes a maximum of 188 milliwatts, according to Fujitsu.
Reducing power was also a goal of NEC Corp.'s 10-Gbit/s serializer/deserializer. Based on 0.15-micron design rules, the device uses a "half-rate" startable-oscillator clock-data recovery scheme in which the VCO operates at 5 GHz. The 0.15-micron transceiver macro consumes 50 mW and takes up less die area than CDR circuits that rely on PLLs and phase interpolators, NEC said.
Rambus Inc. described a high-speed signaling scheme, based on pulse-amplitude modulation (PAM), that ranges from 2.5 to 10 Gbits/s. The approach uses multiple signaling levels to extend interconnect bandwidth by trading off intersymbol interference with received-signal power. The macrocell reaches 10 Gbits/s using a 4-PAM signaling scheme and overcomes signal degradation by applying equalizers on the transmit side and reflection cancellation on the receive side.
The technology can transmit 10-Gbit/s data over 20 inches of backplane with two connectors and two three-inch line cards. Power was measured at 450 milliwatts, according to Rambus.
Seoul National University described a 0.18-micron CMOS test chip at ISSCC that can operate from 2.5 to 10 Gbits/s. The chip can dynamically adjust phase-detector deadband and charge-pump current as a way to stabilize the loop characteristics of CDR and achieve predictable jitter. At maximum speed, the chip consumes 540 mW from a 1.8-V supply.