Enthusiastic support for SystemVerilog alternated with undercurrents of concern at last week's DVCon Design and Verification Conference in San Jose, Calif.
Proponents called SystemVerilog 3.1 the one language that can unite design and verification for RTL chip designers. But others suggested it was just an enhanced version of Verilog that will coexist with many other languages.
Synopsys Inc. strongly backs SystemVerilog 3.1 an emerging specification to which it heavily contributed and has an ambitious road map for simulation and synthesis support. Cadence Design Systems Inc., less enthusiastic, has expressed concern about incompatibility betweenSystemVerilog 3.1 and the existing Verilog IEEE standard. Meanwhile, both Synopsys and Cadence continue to back SystemC for system-level design, despite some inevitable competition between SystemC and SystemVerilog. And the Accellera standards organization is developing both SystemVerilog and a separate Property Specification Language.
But chip designers complain that EDA vendors do not support the existing Verilog 2001 IEEE standard. ASIC designer Cliff Cummings, president of Sunburst Designs, offered a DVCon presentation that showed major Verilog simulators provide spotty and inconsistent compliance to Verilog 2001.
There's little doubt that SystemVerilog represents the biggest overhaul for Verilog since its inception. SystemVerilog 3.0, already approved by Accellera but with scant tool support, adds abstract C-like data types, enumerated types, user-defined types, interfaces, structures and other usability features. But the real change comes with version 3.1, which Accellera expects to roll out at June's Design Automation Conference. It adds an "assert" construct, testbench-generation capabilities derived from Synopsys' OpenVera language, a direct C-language interface and built-in classes for verification. It also promises compliance with Accellera's Property Specification Language.
Thus is born the idea of a single language that can handle both design and verification. In his keynote speech at DVCon, Aart de Geus, chairman and CEO of Synopsys, said SystemVerilog will help close the gap between what can be designed and what can be verified in a reasonable time. "I believe we now have the opportunity to start the design-for-verification age," de Geus said.
While the industry had been divided between VHDL and Verilog in the past, he said, EDA today seems to be backing one language SystemVerilog. De Geus said Synopsys plans to have a synthesis tool for SystemVerilog 3.1 within 12 months.
Consultant Stu Sutherland, president of Sutherland HDL, presented a paper aimed at showing how SystemVerilog 3.1 unites design and verification under a single language. "The idea of SystemVerilog is to move our design work into the 21st century," he said.
But can one language really handle both design and verification? "Design and verification languages have different functions," said Erich Marschner, senior architect at Cadence Design Systems, at a subsequent panel session. "There are different requirements."
Mike McNamara, senior vice president of technology at Verisity, pointed to Esperanto and the Ada programming language as examples of "single languages" that didn't work. "How will SystemVerilog avoid the pitfall of trying to be one language for everybody?" he asked. "Design and verification are different and are best done with different languages."
In the same panel session, Accellera chairman Dennis Brophy warned against speaking of "SystemVerilog ¼ber alles." Brophy, director of strategic development at Model Technology, said his customers want a variety of approaches SystemVerilog, Verisity's "e" language, OpenVera, Cadence's Testbuilder library, the Property Specification Language and others.
Mitch Weaver, vice president of marketing for Cadence's systems verification group, said his company will support future enhancements to the Verilog IEEE 1364 standard. But he expressed concern about incompatibilities between that standard and SystemVerilog 3.1. These include inconsistencies in the initialization of variables, the semantics of "posedge" and "negedge" constructs, record-like constructs, handling of interfaces and various keywords.
Other EDA vendors, including Mentor Graphics, Axis Systems, @HDL, Aldec, Novas, SynaptiCAD and 0-In Design Automation, have pledged support for SystemVerilog 3.0 or 3.1. Synopsys said that SystemVerilog 3.0 support for its VCS simulator has already been deployed to early adopters.
Meanwhile, at a luncheon meeting at DVCon, SystemC advocates said their language was coming into widespread use for both system-level modeling and fast simulation. SystemC recently added a verification library, making it more competitive with SystemVerilog.
"We're trying to avoid language wars," said Stan Krolikoski, chairman of the Open SystemC Initiative. "There's a different user base for the two languages, although some users will have to make a decision as to which one to use."
Still, for ASIC designer Cummings, the issue is not SystemVerilog vs. SystemC but rather, consistent vendor compliance with Verilog 2001. After running compliance test suites on five major emulators, Cummings found that no Verilog 2001 subset is reliably supported by all vendors and that some features in the Verilog 2001 specification have not been implemented by anyone.
Cummings called on EDA vendors to "support the easy stuff" in Verilog 2001, such as ANSI C-style ports, named parameter passing, comma-separated sensitivity lists and attributes. He called for implementation of five enhancements that were listed as the top priorities in a 1996 panel session. These include the "generate" statement, multidimensional arrays, better file I/O, re-entrant tasks and functions, and improved configuration control.
Cummings advised the audience to "keep the pressure up. Make lots of noise. Let the vendors know you need this stuff."