SAN MATEO, Calif. Stacked-die packaging in which IC dice are literally stacked one on top of the other, electrically connected and encapsulated has taken root in the cell-phone handset market as a way to increase memory capacity while reducing footprint. But now the technology is growing in complexity and appears on the way to becoming a serious alternative to system-level IC design.
Indeed, with its ability to combine circuits fabricated in incompatible technologies, minimize wire lengths over an entire subsystem and even employ optical signals, stacked-die technology may accomplish what Moore's Law has thus far prevented: a practical limit to the amount of stuff that goes on one chip.
In the cell-phone market, stacked-die packaging began as a play for reduced board area. Scott Dunagan, product-marketing manager at Intel Corp. (Folsom, Calif.) noted that Japan, in particular, found itself in a real estate crunch: Just as systems designers added features to take advantage of the i-mode network's data capability, industrial designers were reducing the handset's exterior dimensions. Messaging, color displays, interactive games, music synthesis and other features all demanded big increments in memory even as board space shrank. The alternatives were memory integration on an impractical scale or stacked packaging.
Intel and other vendors responded by developing the technology to stack dice in the package. Intel now claims about 20 percent of the total stacked-die market, primarily based on its flash memory business. The company has just announced a series of standard-product stacked-memory devices.
Amkor Technology Inc. (Chandler, Ariz.) is also deeply involved in stacked-package technology and is increasing volume through stacked-die facilities in Korea, Japan and China.
Initially, stacks simply included some flash and an SRAM. Those two technologies do not coexist well in a single process, and flash densities, even with multibit cells, were not keeping up with handset requirements.
But the stacks quickly grew in complexity. Intel now is working with five-level stacks, and that is not the limit.
"We have seen laboratory versions of eight-level stacks," said Bruce Freyman, executive vice president of manufacturing and product operations at Amkor.
The stack is also growing more complex in composition. Intel is adding its Xscale processor to the pile, offering a stack that eliminates the controller chip as well as the memory from the board real estate equation.
Amkor Technology sees a similar trend. "Increasingly, the stacks we are assembling for people include both logic and memory," Freyman said. "Most often, the logic chip is the customer's own ASIC."
The technology necessary for stacked-die is by no means trivial. To begin with, the stack must be planned out in advance so that when the dice are glued onto each other the necessary bonding pads will still be exposed. Once wafers containing the dice have been fabricated, they must be back-ground to thin the dice. Some facilities are now grinding 12-inch wafers to 50 microns so thin that the wafer is highly flexible.
The dice are sawn out of the wafer using conventional mechanical technology and then are glued together with proper alignment. Even this step has a wide variety of potential issues. Some of the dice may have conventional pad rings with landings for wire bonding. Others may have bumps for C4-style bonding. "We see just about every imaginable combination," Freyman said.
Then the chips must be interconnected. Except for the occasional flip-chip on the bottom of the pile, most of the interconnect is still done with wire bonding. This results in a pile of very thin dice, with a spider's web of microscopic wires running between the pad rings at the edges of the dice.
This in itself created a serious technology problem, said Freyman. "We had to learn how to do a reliable wire bond onto a pad on the extreme edge of a die as flexible as paper, sticking out of a stack. It wasn't trivial."
So far, the stacked technology has not wandered far beyond its handset origins. It is beginning to be used in other sorts of very compact devices. But it is still used primarily as a space-saving technology, most often with low- to moderate-performance chips. A fast interface in this arena is 66 MHz.
That could all be changing. Research work at the International Microelectronics Consortium (Leuven, Belgium), for one, is directed at rendering system-on-chip design unnecessary. "This is system-in-package research, and we feel it will be a key competency for the future of the electronics industry," stated Robert Mertens, senior vice president of the microsystems, components and packaging division at IMEC.
The third dimension
Mertens' vision is to address not just real estate needs but the fundamental problems of system-level integration. The real problem in SoC design, according to Mertens, is that at some point you have integrated all the easy digital stuff, and the things left over just won't fit into a manufacturable CMOS chip. You have RF transistors, passive components that require high Q values, high-voltage devices, various kinds of non-SRAM memory, power supplies, antennas and MEMS, for example. Each requires a different fabrication technology and in some cases a material entirely different from bulk silicon.
It makes no sense to attempt to force such elements onto a single die, in Mertens' view. But application requirements may force them into a constrained area.
That brings up a key difference. Today, stacking is about area; tomorrow, it will often be about interconnect performance, Mertens said. The problem of getting a signal across a large die in a 90-nm or 65-nm process is becoming extraordinarily complex. Timing, power and signal integrity issues all escalate. In many cases, adding a third dimension to the problem makes it solvable.
This implies being able to route not just across the surface of a die but straight up or down. And that is exactly what IMEC has in mind.
Researchers there are developing a process for reactive-ion etching vias that pass all the way through the thinned wafer, so that a signal can be routed directly from one die to another in the stack, without having to be moved to the edge first. The technology is aiming for an interconnect density of greater than 10,000 connections per square centimeter.
In the proposed process, signals would be brought to both the top and bottom surfaces of the die and terminated in bumps, much as in conventional C4 processing. Then when the dice are combined into the stack, the corresponding bumps on adjacent dice would be pressed together and fused, creating electrical connections. The through-wafer vias could carry signals straight through a die to permit connections between, say, the first and third dice in a pile.
Other technologies are being examined for interconnect purposes. At the International Solid-State Circuits Conference, a research team from the Georgia Institute of Technology Microelectronics Research Center (Atlanta) described a system of flexible polymer pillars and sockets that could simultaneously carry electrical and optical signals between layers in a die stack.
Such pillar-and-socket arrays, the team reported, could be fabricated with pitches finer than 10 micrometers, permitting enormous interconnect densities between dice.