SAN FRANCISCO Three novel uses of non-silicon materials in semiconductors were examined at a Wednesday (Feb. 12) session at the International Solid-State Circuits Conference here.
In the session's first presentation, Daniel Shepard, founder of Nup2 Inc. (North Hampton, N.H.), described a non-photographic lithography process that is inherently self-aligning at all layers and could, potentially, exploit existing DVD manufacturing tools to produce integrated circuits with feature sizes as low as 10 nm.
In the process, a topology is created on a polymer substrate by injection moulding. Other processes could be used, Shepard said, but injection moulding permits use of existing DVD cluster tools. Then successive layers of material semiconducting films, insulators and etch-control films are deposited over the surface.
Using a combination of planarization techniques and selective etching, these films are removed from high spots and left in place in designated areas to form patterns of semiconductor, insulator and metal.
In a demonstration project, Nup2 has created a diode array memory using amorphous silicon diodes with a pitch of 4 micrometers.
Shepard claimed that the process, by applying successive steps, had the potential to produce thin-film transistors as well as diodes and metal, and could eventually produce very fine geometry integrated circuits on polymer substrates with only moulding, planarization and etch steps, without the need for photolithography.
In a second paper, Philip Wong of IBM Research (Yorktown Heights, N.Y.), summarized progress to date in the construction of field-effect transistors using carbon nanotubes. The devices are formed by first creating a semiconducting nanotube by chemical vapor deposition, then establishing contacts at either end of the tube, and finally, creating an insulated gate over, under or around the middle of the tube, between the contacts.
Wong said that current work produces quite acceptable small FETs with surprisingly high currents. Trend lines suggest that devices with 50-nm geometry and performance comparable to the best 50-nm MOSFETs could be done even without further optimizations of device performance.
But optimizations may be in order, Wong said. His research suggests that current techniques create Schottky diodes at the ends of the tube. If these diodes could be eliminated, both series resistance and overall device performance should increase dramatically, he said.
Finally, Muhannad Bakir, from the Microelectronics Research Center at the Georgia Institute of Technology (Atlanta), discussed recent advances in creating both electrical and optical interconnect arrays over the surface of ICs by fabricating polymer pillars and sockets. The pillars on one device fit into the sockets of another device to establish the connection, which can be electrical, optical, or both simultaneously. Pillars measuring 5 micrometers in diameter and set on a 12-micrometer pitch were demonstrated.