TOKYO NEC Corp. has developed a single-chip parallel processor dedicated to image recognition. The chip, which processes 50.2 giga-operation per second, is about four times faster than a 3-GHz processor for PCs, but consumes about one tenth as much power, said NEC, which described the processor at the IEEE International Solid-State Circuits Conference on Monday (Feb. 10).
Fabricated in 0.18-micron seven-layer metal CMOS, the processor die has 32.7 million transistors and measures 11 mm on a side. The chip's parallel structure consists of one-hundred and twenty-eight 8-bit RISC processing elements and a 16-bit RISC processor that functions as a controller. Each processing element operates at 100 MHz to lower power consumption, and each has an exclusive 2-k memory to store image data.
The processor was intended as an improvement over existing approaches to image recognition, including the use of general-purpose processors, DSPs, ASICs or FPGAs. None of these approaches fully satisfy the requirements of high speed, compact size and low power consumption, said Shinichiro Okazaki, principal researcher of NEC Multimedia Research Laboratories.
NEC engineers developed an algorithm that uses parallel PEs to process an image line by line. The software is written in C. "Even described by the high-level language, not assembler, the processor can realize high performance," Okazaki said. The chip's power consumption is similar to a PDA's, but its performance is similar to what can be achieved by four PCs, he said.
NEC expects to improve the image processor's implementation. "We fabricated it on the 0.18-micron process, which is not the most advanced process we have," Okazaki said. "The resultant 11 x 11-mm size is too large." NEC will need at least one more year to prepare the chip for practical use, said Takao Nishitani, general manager of NEC's Multimedia Research Laboratories.