San Mateo, Calif. - A video bit-rate controller chip from ViXS Systems Inc. has been included in a major Toshiba reference design, the Toronto-based company said last week.
XCode, which is said to distribute broadcast-quality video over local, wired or wireless Internet Protocol networks, has been integrated into the AVM79R reference design from Toshiba America Electronic Components Inc. (Santa Clara, Calif.). The design targets digital set-top boxes, media gateways and other multimedia platforms that manage networked home entertainment products.
ViXS' design win rewards the startup for a substantial fast-track effort that combined a breakthrough algorithm with conservative decisions on process and methodology choices. The formula seems to have clicked for ViXS and it's being examined by an increasingly wide range of other design teams facing similar market situations.
The XCode chip receives up to eight MPEG-1, -2 or -4 bit streams and selectively reduces their bit rates to fit them through the available bandwidth of a downstream network. The output bit streams are entirely MPEG-compliant, so they don't need special decoding hardware. Just as important, the bit-rate reduction is done in a way that selectively reduces image detail rather than dropping frames, tinkering with the motion estimation of the original source or other tactics that can be annoyingly obvious to the viewer.
"We can reduce the bit rate by up to 50 percent-to 3 Mbits/second-without dropping the frame rate below full 30 frames/s," said Hugh Chow, vice president of engineering and co-founder of the company. That puts smooth video delivery within reach of even partially loaded 802.11 networks.
Actual network management is done by external software, which monitors available bandwidth and directs the XCode chip to produce a specified bit rate for a particular video stream. The chip, using a proprietary algorithm that is ViXS' secret sauce, partially decodes each MPEG stream, selectively manipulates the resolution or granularity of some frames, and re-encodes each stream.
The hardware necessary to do that includes a MIPS core and a number of other complex blocks, none of which ViXS is willing to describe while patents are pending. But the overall design flow gives an interesting picture of a design team working under tight present-day constraints.
One key element in the design process was to be conservative from the outset. ViXS decided to go with United Microelectronics Corp.'s 0.18-micron standard CMOS process, and with a customer-owned-tooling flow that was, if not at all state-of-the-art, quite familiar to the startup's engineers. "Schedule had to be our first priority," Chow explained. So choices were made that reduced design risk or learning time without putting the performance goals out of reach.
Accordingly, the design started out as algorithms on paper. It moved quickly from there to an executable C++ implementation. This wasn't just a software model, Chow emphasized. The designers created some new classes to permit modeling of hardware and timing issues in their code and produced a very hardware-aware executable source.
The architects wrung out the code to produce as full a block-level emulation of the intended hardware as possible, and simultaneously hand-converted it into RTL code for the chip design. A separate team converted the code into a Virtex-II FPGA implementation. The FPGAs, HDL simulations and C++ model could all be checked against one another using a rapidly emerging verification suite.
But the FPGA emulation had a major advantage: It was sufficiently fast to serve as a software development platform. Not only did this get the software team going early, but it proved invaluable in verification. "By the end of the project, the software developers had found bugs that had escaped the hardware verification effort," Chow said. "Any one of a few of them would have ruined the first tapeout. So I have to say that this level of verification was extremely important to us."
While Chow recommends the technique, he does point out that it requires forethought. "If you don't plan the RTL from the beginning with the idea of doing an FPGA implementation, you will have headaches later," he warned. In particular, the RTL structure has to recognize that the design will be fitted into discrete FPGAs, and must be partitionable to accommodate that.
During the RTL and FPGA developments a separate part of the team produced a full verification suite. The team relied on standard functional verification techniques because this approach was in line with their experience and because it provided a reference path back to the golden C++. Assertion-based methods were not used.
For physical design, Chow once again made the conservative decision. "We decided to employ a flat design approach using Silicon Ensemble," he said, "because that approach fit our expertise." The entire 5 million-gate design would not fit, so it had to be manually partitioned for place and route. Again, forethought saved headaches.
The team did repeated trial layouts, using full placements of the external intellectual property-primarily I/O library elements, memories and the MIPS core, the blocks for which the RTL was essentially done-and estimated dummy blocks for the pieces that were not yet complete. This provided a continuously improving view of the full chip layout and of interconnect-related timing or congestion issues before they locked in a final placement.
The result was relatively few timing issues in the final build, Chow said. First silicon proved functional. And the bottom line was simple: from clean sheet of paper to completed design in 12 months, and silicon in the hands of first customers in 18 months.
It's a time when marketing opportunities can be transient, and when a design flow has to deliver on the first iteration. But today, even challenging performance goals can often be attacked with architectural or algorithmic breakthroughs rather than with a leading-edge process. In such an environment, going with a stable process and with a familiar flow can be an important contribution to success, not just in design but in the survival of the venture.